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Reducing Device-Level Substrate Noise Coupling Using a Micro-Ring in CMOS-Based ICs

IP.com Disclosure Number: IPCOM000128961D
Publication Date: 2005-Sep-22
Document File: 2 page(s) / 69K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses a micro-ring (i.e. guard ring) to mitigate substrate noise (SN) coupling among various devices in a silicon IC. Benefits include a solution that can be applied to any CMOS IC.

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Reducing Device-Level Substrate Noise Coupling Using a Micro-Ring in CMOS-Based ICs

Disclosed is a method that uses a micro-ring (i.e. guard ring) to mitigate substrate noise (SN) coupling among various devices in a silicon IC. Benefits include a solution that can be applied to any CMOS IC.

Background

A major source of SN is the noise current injected from the source and drain of PMOS and NMOS devices into the substrate. This noise propagates through the substrate and couples with other PMOS or NMOS devices. The mechanism for this coupling is either the local variation of bulk voltages underneath the channel (i.e. back gate effect), or the noise capacitively coupled to the source and drain.

There are different mechanisms for reducing the SN coupling. One common method is to surround the sensitive and aggressor circuit blocks with P+ or N+ guard rings that are tied to the ground or the highest voltage source available, respectively. The P+ guard ring collects the noise current resistively before it propagates through the substrate. The N+ guard ring blocks the noise current by a reverse bias in the p-n junction.

General Description

The disclosed method uses a micro-ring at the device level to mitigate SN coupling among various devices in a silicon IC. The disclosed method uses the bulk node of the PMOS and NMOS devices as a micro-ring. Figure 1 shows the layout of a typical multi-finger NMOS device. Both measurements and simulations suggest that the bulk node connected to an...