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Methode und Anordnung zur On-Chip-Messung der IO Schwankungen durch Wiederverwendung einer DLL

IP.com Disclosure Number: IPCOM000128993D
Published in the IP.com Journal: Volume 5 Issue 10A (2005-10-25)
Included in the Prior Art Database: 2005-Oct-25
Document File: 3 page(s) / 84K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Innovative High-Speed DRAM (Dynamic Random Access Memory) products make great demands on modern testers. Often the increase of velocity of the DRAMs is greater than with the testers available on the market. Many tests can be implemented with low frequencies, some not. To the latter it belongs to the determination of the different deceleration times at the input/outputs. Now these are to be determined by means of slow testers. Registered DLLs (Delay Locked Loop) are generally well known and are used in a wide range. In each Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) there is such a DLL. The block diagram in figure 1 shows a DLL. The idea is the reuse of DLL (which has a wide delay range and a high resolution together) to measure/compare propagation delays of OCD and RCV. This approach makes heavily reuse of the existing DLL. The advantage is that it does not need big circuits per IO (input/output). The disadvantage is that it needs an additional balanced clock tree (blue) and tree mismatches (and redriver) decrease the accuracy of the measurements.

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Methode und Anordnung zur On-Chip-Messung der IO Schwankungen durch Wiederverwendung einer DLL

Idea: Patrick Heyne, DE-Munich; Maksim Kuzmenka, DE- Munich; Roman Mayr, DE- Munich

Innovative High-Speed DRAM (Dynamic Random Access Memory) products make great demands on modern testers. Often the increase of velocity of the DRAMs is greater than with the testers available on the market. Many tests can be implemented with low frequencies, some not. To the latter it belongs to the determination of the different deceleration times at the input/outputs. Now these are to be determined by means of slow testers.

Registered DLLs (Delay Locked Loop) are generally well known and are used in a wide range. In each Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) there is such a DLL. The block diagram in figure 1 shows a DLL.

The idea is the reuse of DLL (which has a wide delay range and a high resolution together) to measure/compare propagation delays of OCD and RCV.

This approach makes heavily reuse of the existing DLL. The advantage is that it does not need big circuits per IO (input/output). The disadvantage is that it needs an additional balanced clock tree (blue) and tree mismatches (and redriver) decrease the accuracy of the measurements.

Clock tree

Two matched clock trees will be provided to every IO channel. One clock has a fixed phase (blue tree). The other one is the clock provided by the DLL and its time shift can be adjusted. In a first operation mode the delay of the DLL...