Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Ultra Low Power DFF (ULP-DFF, Ultra Low Power-Delay Flip-Flop)

IP.com Disclosure Number: IPCOM000129014D
Original Publication Date: 2005-Oct-25
Included in the Prior Art Database: 2005-Oct-25
Document File: 1 page(s) / 85K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In current electronic applications, a Flip-Flop (Flip-Flop = bistable multivibrator) is a pulsed digital circuit, capable of serving as a one-bit memory. A delay flip-flop (DFF) can be interpreted as a primitive delay line or so called zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

S

Ultra Low Power DFF (ULP-DFF, Ultra Low Power-Delay Flip-Flop)

Idea: Alessandro Pesci, AT-Graz

In current electronic applications, a Flip-Flop (Flip-Flop = bistable multivibrator) is a pulsed digital circuit, capable of serving as a one-bit memory. A delay flip-flop (DFF) can be interpreted as a primitive delay line or so called zero-order hold, since the data is posted at the output one clock cycle after it arrives at the input.

The following idea introduces a very efficient way to implement a transistor level of a Flip-Flop, drastically reducing the power consumption. Thereto, a fixed, additional number of 10 transistors realize the gate at the clock of the Flip-Flop. This set-up consumes 10 times less than current Flip- Flops and permits to avoid the gated clock insertion during synthesis. The enabling of the clock is obtained by a XNOR (XNOR, eXclusive NOR gate). The clock is propagated only when the result of the XNOR is zero. If the result is 1, the clock is forced to be 1, too. Forcing the clock to 1 instead of forcing it to 0 avoids problems at moments of new incoming data.

Fig. 1: ULP-DFF

© SIEMENS AG 2005 file: ifx_2005J53161.doc page: 1

[This page contains 1 picture or other non-text object]