Browse Prior Art Database

ESD Protection for EFUSE Pads

IP.com Disclosure Number: IPCOM000129028D
Original Publication Date: 2005-Oct-25
Included in the Prior Art Database: 2005-Oct-25
Document File: 3 page(s) / 46K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The presented idea addresses the challenge of protecting the supply pad cell for electrical fuses (EFUSE-pad) against current surges as occurring during electrostatic discharge (ESD). A typical EFUSE circuit is shown in Fig. 1. Electrical fuses are usually integrated into VLSI (Very Large Scale Integration) semiconductor ICs (Integrated Circuits) by using a tapered stripe of conducting material (metal, poly-silicon, etc.), so that for a given current level (I_fuse) the weak link at the most narrow spot of the stripe is thermally destroyed, thus changing the resistance of the EFUSE stripe. The fuse state of an EFUSE can be read out by a control circuit, in a simple case as shown in Fig. 1. The EFUSE-supply pad is providing the voltage and current for the fuse process, while the control block enables the fuse current by opening the NMOS (Negative Channel Metal Oxide Semiconductor) switch in series to the EFUSE. The required FUSE voltage V_fuse is usually significantly higher than the core supply voltage of the IC, (e.g. V_efuse = 4V for a core supply voltage of 1.8V), which results in a serious problem for ESD protection of the EFUSE supply pad, as described in the following:

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ESD Protection for EFUSE Pads

Idea: Dr. Martin Wendel, DE- Munich; Dr. Martin Streibl, DE- Munich; Dr. Kai Esmark, DE-Munich;

Dr. Gernot Langguth, DE- Munich

The presented idea addresses the challenge of protecting the supply pad cell for electrical fuses (EFUSE-pad) against current surges as occurring during electrostatic discharge (ESD).

A typical EFUSE circuit is shown in Fig. 1. Electrical fuses are usually integrated into VLSI (Very Large Scale Integration) semiconductor ICs (Integrated Circuits) by using a tapered stripe of conducting material (metal, poly-silicon, etc.), so that for a given current level (I_fuse) the weak link at the most narrow spot of the stripe is thermally destroyed, thus changing the resistance of the EFUSE stripe. The fuse state of an EFUSE can be read out by a control circuit, in a simple case as shown in Fig. 1. The EFUSE-supply pad is providing the voltage and current for the fuse process, while the control block enables the fuse current by opening the NMOS (Negative Channel Metal Oxide Semiconductor) switch in series to the EFUSE.

The required FUSE voltage V_fuse is usually significantly higher than the core supply voltage of the IC, (e.g. V_efuse = 4V for a core supply voltage of 1.8V), which results in a serious problem for ESD protection of the EFUSE supply pad, as described in the following:

To provide ESD protection as demanded by today's industry standards, ESD protection elements have to be added to the EFUSE supply pad as shown in Fig. 1. In a typical ESD event currents of 1-5A are flowing into or out of the EFUSE supply pin. To avoid a damage of the circuit the ESD protection devices have to provide a low-ohmic ESD current shunt path to the supplies, so that a certain critical voltage level is not exceeded.

In the case of Fig. 1 and making a worst case assumption that the NMOS switches are not closed during ESD, the maximum voltage at the EFUSE pad must not significantly exceed the fuse voltage V_fuse, otherwise EFUSEs will be fused by the ESD current randomly and the IC will be destroyed.

On the other hand for the fusing process, the ESD protection must not turn on at or around V_fuse.

These two constraints leave a very tight design window to fit in ESD protection with an acceptable protection performance. This either leads to very high ESD device development effort to find a suitable protection device or a limited ESD performance of the EFUSE supply pad.

The core of the idea is to exploit a circuit feature of a class of EFUSE pads for ESD protection. This class of EFUSE pads as sketched in Fig. 2 is equipped with an additiona...