Browse Prior Art Database

Method for using low cost CMOS technology for high side drivers

IP.com Disclosure Number: IPCOM000129125D
Published in the IP.com Journal: Volume 5 Issue 10A (2005-10-25)
Included in the Prior Art Database: 2005-Oct-25
Document File: 5 page(s) / 644K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In circuit arrangements for driving a N-Type-Half-Bridge Driver (Fig. 1 - 1), which consists of a series connection of two N-Type MOS (Metal Oxide Semiconductor) switches, a High Side Driver (Fig. 1 - 2) drives the gate of the ground connected switch and a Low Side Driver (Fig. 1 - 3) drives the gate of the battery connected switch. The High Side Driver is supplied by a voltage, referred to SW (Fig. 1), and buffered by the Bootstrap capacitor. A Level-shifter is needed to translate ground referred signals that derive from the Control Circuit (Fig. 1 - 4) to SW referred signals. To use low cost CMOS technology in this assembly, fast transitions (some 10 V/ns) of the SW node (Fig. 1) lead to a latch up. To explain the “latch up effect”, in Fig. 2, a simplified cross section of the CMOS inverter of the High Side Driver is shown. Two main components are responsible for the ”latch up effect”:  The big parasitic junction capacitance Csub (Fig. 2) between the pocket and the substrate  The also big resistance RN (Fig. 2) between the N-pocket and the contact A transition of the SW (Boot) node (Fig. 2) from high to low causes an AC current of several mA ( ) that implicates a voltage drop over the N-Pocket resistance RN (Fig. 2) and forward-biases the parasitic PNP. That PNP activates the parasitic NPN which provokes the device to latch. An innovative idea proposes to separate the system shown in Fig. 1 into two parts/chips (Fig. 3): High side part for itself and Low side part including the controller. Using a chip on chip or chip by chip solution, the problem of latching up is solved also using low voltage and/or cheap CMOS technology.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 5

S

Method for using low cost CMOS technology for high side drivers

Idea: Andrea Logiudice, IT-Padova; Giovanni Capodivacca, IT-Padova

In circuit arrangements for driving a N-Type-Half-Bridge Driver (Fig. 1 - 1), which consists of a series connection of two N-Type MOS (Metal Oxide Semiconductor) switches, a High Side Driver (Fig. 1 - 2) drives the gate of the ground connected switch and a Low Side Driver (Fig. 1 - 3) drives the gate of the battery connected switch. The High Side Driver is supplied by a voltage, referred to SW (Fig. 1), and buffered by the Bootstrap capacitor. A Level-shifter is needed to translate ground referred signals that derive from the Control Circuit (Fig. 1 - 4) to SW referred signals. To use low cost CMOS technology in this assembly, fast transitions (some 10 V/ns) of the SW node (Fig. 1) lead to a latch up. To explain the "latch up effect", in Fig. 2, a simplified cross section of the CMOS inverter of the High Side Driver is shown. Two main components are responsible for the "latch up effect":

The big parasitic junction capacitance Csub (Fig. 2) between the pocket and the substrate

The also big resistance RN (Fig. 2) between the N-pocket and the contact

A transition of the SW (Boot) node (Fig. 2) from high to low causes an AC current of several mA ( mA ns

       V pF dt

= ) that implicates a voltage drop over the N-Pocket resistance RN (Fig. 2)

and forward-biases the parasitic PNP. That PNP activates the parasitic NPN which provokes the device to latch.

An innovative idea proposes to separate the system shown in Fig. 1 into two parts/chips (Fig. 3): High side part for itself and Low side part including the controller. Using a chip on chip or chip by chip solution, the problem of latching up is solved also using low voltage and/or cheap CMOS technology.

The high side chip is connected to the SW node via the substrate and the N-pocket is connected to the BOOT node. Since BOOT and SW are shorted by CBOOT (Boot Capacitor), there is no voltage change across the parasitic capacitance CSUB and no capacitive current that could cause a la...