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Interpolated phase alignment via oversampling

IP.com Disclosure Number: IPCOM000129169D
Original Publication Date: 2005-Sep-29
Included in the Prior Art Database: 2005-Sep-29
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Abstract

A method of oversampling data received on a high-speed serial interface of an FPGA overcomes the limitations of the phase adjustment mechanism included in the receivers. The limited range of phase adjustment is compensated by double sampling of incoming data, in order to enlarge the total range of possible receive clock phases.

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Interpolated phase alignment via oversampling

Several FPGA families support very high bandwidth interfaces by implementing high speed serial I/Os. This enables efficient chip-to-chip interconnections, including the direct attachement of high-bandwidth memories incorporating serial interfaces.

In order to optimize data reception, most serial I/Os in FPGAs include a phase adjustment mechanism, so that incoming data can be sampled in a stable region of the data cycle. The typical way to control this mechanism is to move the phase of the sampling clock in the receiver to evaluate the window of stable data, when receiving a calibration signal alternating between 0 and 1, and position the clock phase in the center of this window. However, some FPGA serial I/Os present limitations in this mechanism. A particular FPGA family has a phase adjustment function limited to +/- 15 steps of 0.02 UI each, leading to a phase adjustment range of 0.6 UI, i.e. only 60% of the data cycle. This can make some phase adjustments difficult to control, particularly in cases where the period of stable data (eye width) is relatively short.

    This is what occured in an application where the FPGA communicates with a high-speed memory through 5 Gbps serial interfaces. In the 200 ps data cycle times, the eye width is only 140 ps because of jittery data transitions that occur in a 60 ps window.

    If the receive clock happens to be enough centered in the data eye, then the phase adjust can be controlled so as to position the sampling clock in a stable data region. In the figure below, the receive clock is located 4 ps after the center of the data eye (shown as light gray region). The phase adjust step is 0.02 UI = 4 ps. Playing with the phase adjust mechanism from -15 steps (-60 ps, italicized) to +15 steps (+60 ps, italicized) will not detect any data transition. Then it would be appropriate to keep the original clock position, i.e. phase = 0 ps (underlined), which would provide a 74 ps margin before, and 66 ps margin after the sampling time.

-60 ps

Data Cycle = 200 ps

Eye width = 140 ps

0 ps

Data transition = 60 ps

DATA

CLK

74 ps

66 ps

+60 ps

Fig. 1

But if the receive clock happens not to be centered in the data eye, then the apparent period of stable data is shrinking, making the sampling control more difficult.

1

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In the figure below, the receive clock is located 61 ps after the center of the data eye. A phase adjustment of -15 steps (-60 ps) will not detect any data transition, but a phase adjustment of +3 steps (+12 ps) will detect data transition at the end of the data eye. This means that data is seen stable from 60 ps before, to 8 ps after receive clock edge. Choosing a sampling time in the center of this window of phase exploration, by adjusting the phase to -6 steps (-24 ps) would lead to dangerously unbalanced margins: 107 ps before sampling time, but only 33 ps after sampling time.

DATA

CLK

Data Cycle = 200 ps

Eye width = 140 ps

-60 ps

Data trans...