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Browse Prior Art Database

Bitline Strapping

IP.com Disclosure Number: IPCOM000129184D
Original Publication Date: 2005-Oct-25
Included in the Prior Art Database: 2005-Oct-25
Document File: 1 page(s) / 22K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The high bitline resistance in TwinFlash technology is limiting the programming window of the memory cell. Therefore only a limited number of program or erase cycles without data loss can be guaranteed. Presently known processes reducing the bitline resistance, e.g. AlCu RIE (Reactive Ion Etching) process, are not yet developed for the desired pitch and therefore not available for current products. By reducing the bitline resistance the production costs of memory products can be reduced. The following idea proposes to reduce the high bitline resistance indirectly by using an additionally metal layer in the array for a bitline strapping, like shown in fig. 1 (metal 1). By stripping only a half of the bitline length the process complexity is reduced and the double bitline pitch is used for the extra metal layer. In case of low wordline resistance it is not necessary to use the metal 1 for a wordline strapping, at least if the wordline drivers are positioned on both sides of the array.

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Bitline Strapping

Idea: Joachim Deppe, DE-Dresden

The high bitline resistance in TwinFlash technology is limiting the programming window of the memory cell. Therefore only a limited number of program or erase cycles without data loss can be guaranteed. Presently known processes reducing the bitline resistance, e.g. AlCu RIE (Reactive Ion Etching) process, are not yet developed for the desired pitch and therefore not available for current products. By reducing the bitline resistance the production costs of memory products can be reduced.

The following idea proposes to reduce the high bitline resistance indirectly by using an additionally metal layer in the array for a bitline strapping, like shown in fig. 1 (metal 1). By stripping only a half of the bitline length the process complexity is reduced and the double bitline pitch is used for the extra metal layer. In case of low wordline resistance it is not necessary to use the metal 1 for a wordline strapping, at least if the wordline drivers are positioned on both sides of the array.

Metal 1 is used to do a bitline strapping to reduce the bitline resistance of metal 0, e.g. by using the double array pitch of metal 0. Every M0 bitline is strapped to M1 by a C1 via close to the associated select transistor and close to the middle of the array.

With this approach the M0 bitline resistance is reduced by nearly 50%. In this manner the number of select transistors is reduced, the chip size is minimized by a considerabl...