Browse Prior Art Database

Floating Polysilicon ESD NFET

IP.com Disclosure Number: IPCOM000130107D
Original Publication Date: 2005-Oct-11
Included in the Prior Art Database: 2005-Oct-11
Document File: 6 page(s) / 89K

Publishing Venue

IBM

Abstract

Fully silicided NFETs are not capable of handling ESD currents. Previous known solutions involve desigining NFETs that are capable of handling ESD events with silicide blocking on their source and drain regions. This solution consumes larger area. The proposed solution utilises a novel way of designing silicided NFETs which are capable of handling larger ESD currents.

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Floating Polysilicon ESD NFET

Disclosed is a method for forming a high current handling, low area consuming fully silicided NFET for use as an Electro-Static Discharge (ESD) protection device in a CMOS logic technology.

Floating Polysilicon, perpendicular to the NFET gate, is designed between contacts on the source and drain regions of the ESD NFET. This lower space consuming structure is seen to handle larger ESD current and is a potential solution. An approximate space saving of ~50% per I/O can be realised. There is also no need for the additional OP mask which would be required if the source and the drain regions of the NFET were to be silicide blocked.

Figure.1 shows a typical NFET-based Non-self protecting ESD strategy. The goal of ESD protection devices is not only to provide an non-destructive, efficient and effective path for discharge of an ESD event, but also to keep the pad voltage as low as possible and hence prevent snapback and/or gate oxide breakdown of driver NFET/PFET drivers and FET receivers.

Figure.2 shows the cross-section of a silicide-blocked grounded gate ESD NFET. During a positive mode ESD event, the n+ drain/SX junction breaks down and results in avalanche generation of carriers. The holes collected by the substrate raises the substrate potential (Vsub=Isub*Rsub), eventually resulting in forward bias of the source/SX junction and turning on of the source-substrate-drain NPN BJT. The silicide-blocking region on the source and drain is necessary to provide ballasting resistance to ensure uniform current flow.

Figure.3 shows the I-V characteristics of a silicide-blocked grounded gate ESD NFET. Vt1 and Vsp in the figure refers to the turn-on of the lateral npn BJT and the sustaining voltage respectively. Though a similar I-V characteristic is desired from a fully silicided grounded gate ESD, typical fully silicided devices tend to fail destructively immediately after snapback without handling any or much current.

The motivation for this disclosure is to enable fully silicided NFET drivers handle some current during an ESD event, thus enabling ESD protection with diodes or NFETs without the need for silicide-blocked or stacked NFETs. With this disclosure the IO pad voltage can be allowed to a slightly higher voltage than in the case of a fully silicided NFET. Silicide-blocked NFETs also require an additional OP mask, which is a cost adder when the OP mask is not used in the design. A smaller driver area and a lower capacitive loading is also accomplished without the use of silicide blocked NFETs or stacked NFETs.

Figure.4 shows the proposed layout design of the Floating Polysilicon ESD NFET, where the floating polysilicon is designed between the contacts on the source and drain regions. The layout regions are as as follows: Red: N+ diffusions, Green: Polysilicon,

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White: Contacts.

Prior art have either involved (1) increasing the drain/source contact to poly space, (2) isolation slots designed i...