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Wide Range Level Translator with Enable Input

IP.com Disclosure Number: IPCOM000130108D
Original Publication Date: 2005-Oct-11
Included in the Prior Art Database: 2005-Oct-11
Document File: 3 page(s) / 174K

Publishing Venue

IBM

Abstract

A voltage level translator is described which operates over a wide range and includes an integral logic gate. Switching speed is enhanced by cut off devices in the cross coupled latch devices.

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Wide Range Level Translator with Enable Input

Voltage level translators are inherently slow. When an enable/disable feature is added, an additional gate delay is added to an already slow element.

The circuit in figure 1A is a 6-device level translator with an integral enable feature. The input signal IN_GND swings between GND and Vdd of around 1 Volt for example. This input signal is translated to a negative low level, VWL ( typically -0.5V) as in the word decode system of an imbedded memory array. A disable/enable feature is needed to select a sub block of a group using a common global wordline. The enable/disable feature can be added with a standard NAND / NOR gate, but this adds another gate delay in an already slow circuit block. A prior art circuit implementation is shown the right side of figure 1B.

Low voltage operation is improved in the disclosed circuit by addition of N2 and N3, which allow the PFET pullup devices P3 and P0 to raise cross coupled gates N0 and N1 more completely at low Vdd. This greatly improves performance.

The enable function is made by devices P1 and N4 which force output OUT_VWL to Vdd when ENAB_P is at GND. A path from output node "B" to VWL is made through N3 by forcing gate node "A" to Vdd by NOR gate I1.

A performance comparison to a prior art 4-device level translator with an added enable gate is shown in Figure 2 as a function of VWL. This HSPICE simulation was done over Vdd=.88 and VWL = -0.1 to -0.7 Volts. This disclosed circ...