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A Channel Length and Drain-Source Resistance Extraction Method for MOSFET’s

IP.com Disclosure Number: IPCOM000130299D
Published in the IP.com Journal: Volume 5 Issue 11A (2005-11-25)
Included in the Prior Art Database: 2005-Nov-25
Document File: 10 page(s) / 1M

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

The effective channel length ( ) and drain-source resistance ( ) of MOSFET’s are of utmost importance for circuit modeling, process monitoring and device design. There have been several attempts to extract the MOSFET’s channel length in the submicron region where many difficulties arise due to the strong variation of mobility with gate voltage, higher influence of graded source and drain doping profiles, and the lithography near to the optical resolution limit. Although most circuit models do not implement a gate-voltage-dependent channel length, it is known that both, the channel length reduction parameter ( ) and the drain-source resistance vary with gate-voltage. That is why it is focused on extracting the gate-voltage-dependent channel length reduction parameter and the drain-source resistance while the drain-source resistance is uniquely separated from the channel resistance. The basic principles of this approach are similar to those of the so called improved “shift and ratio” method but in addition to the short and long channel devices a reference device, which is the second longest device, is required. Further, in the new method differentiation of the externally measured total resistance ( ) avoids the hindrance of the large errors arising from measurements. A method is known, in which three devices with different gate-lengths are implemented. In that model it is assumed that the drain-source resistance can be ignored in the long channel device in comparison with the channel resistance and minimized the mean-square error between the drain-source resistances of other two devices. There are two major shortcomings with their approach. The first is that the drain-source resistance for LDD devices cannot be ignored especially at high gate-voltages. The second is assumption of a unique Rds and a constant for all devices.

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S

A Channel Length and Drain-Source Resistance Extraction Method for MOSFET's

Idea: Mojitaba Joodaki, DE-Munich

The effective channel length ( ) and drain-source resistance ( ) of MOSFET's are of utmost

importance for circuit modeling, process monitoring and device design. There have been several attempts to extract the MOSFET's channel length in the submicron region where many difficulties arise due to the strong variation of mobility with gate voltage, higher influence of graded source and drain doping profiles, and the lithography near to the optical resolution limit. Although most circuit models do not implement a gate-voltage-dependent channel length, it is known that both, the channel length reduction parameter ( ) and the drain-source resistance vary with gate-voltage. That

is why it is focused on extracting the gate-voltage-dependent channel length reduction parameter and the drain-source resistance while the drain-source resistance is uniquely separated from the channel resistance.

eff

L ds

R

  = ∆

eff

LLmask L

-

The basic principles of this approach are similar to those of the so called improved "shift and ratio" method but in addition to the short and long channel devices a reference device, which is the second longest device, is required. Further, in the new method differentiation of the externally measured total resistance ( ) avoids the hindrance of the large errors arising from measurements.

tot

R

A method is known, in which three devices with different gate-lengths are implemented. In that model it is assumed that the drain-source resistance can be ignored in the long channel device in comparison with the channel resistance and minimized the mean-square error between the drain-source resistances of other two devices. There are two major shortcomings with their approach. The first is that the drain-source resistance for LDD devices cannot be ignored especially at high gate-voltages. The second is assumption of a unique Rds and a constant L

∆ for all devices.

The externally measured total channel resistance ( ) in the linear region is:

tot

R

(1) ) (

    V R -

'

      ds tot V

t

   = =

 V f L V R V V R V R I

    g ch g ds ds

      eff g ds

g

t

  ) (

+

(

   = -

)

  ) (

+

V

' ds

in which is the external voltage applied between drain and source which is usually kept below 100

mV, is drain-source current, is the gate-voltage-dependent drain-source resistance,

is the channel resistance, is the threshold voltage, and f is a general function of gate

voltage. The key assumption behind (1) is that the effective mobility

I )

( g

Rds V

ds

  V R - t

( t g ch V

)

V

µ is a common function of
. If we assume is the same for short and long devices, then the measured 's for

the three devices are:

eff

( t

Vg V

- )

( g

Rds V tot

)

R

(2)

 V f L V R R -

s tot V

=

s ds

  ) (

s eff g

+

g

(

 s t

)

(3)

 V f L V R R -

r tot V

=

r ds

  ) (

r eff g

+

g

(

 r t

)

(4)

 V f L V R R -

l tot V

=

l ds

  ) (

l eff g

+

(

g

 l t

)

R

in which s, r, and l stands for short, reference, and long device...