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Browse Prior Art Database

Active Bootstrap Charging Diode

IP.com Disclosure Number: IPCOM000130305D
Original Publication Date: 2005-Nov-25
Included in the Prior Art Database: 2005-Nov-25
Document File: 3 page(s) / 191K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In a gate driver circuit the bootstrap capacitor CBOOT is charged by a diode, which has to be integrated into the circuit (see Fig. 1). Up to now, a pnp bipolar transistor can be used if diode connected to act as a bootstrap diode, getting a voltage loss of around the base emitter on voltage =~ 0.8 V or more (depending on the technology). In this situation if the charging (PVCC) voltage is 5 V, the bootstrap capacitor can reach only 4.2 V (or less) over the lower supply voltage (PHASE level, in this case). This means that the maximum internal supply voltage can be 4.2 V; but if we consider ripple and spikes this could be even lower. The circuit behavior could be worsened. With the use of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is possible to decrease the voltage loss as the VDS,sat of a MOSFET is lower than a VBE,on of a bipolar, especially when overdrive is sufficiently high. If VDS is around 0.2-0.3 V, an increase in the voltage headroom is obtained available of 0.5 V.

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Active Bootstrap Charging Diode

Idea: Giovanni Capodivacca, IT-Padova; Nicola Florio, IT-Padova; Jian Rong Huang, TW-Chupei

City; Riccardo Pittassi, IT-Padova

In a gate driver circuit the bootstrap capacitor CBOOT is charged by a diode, which has to be integrated into the circuit (see Fig. 1).

Up to now, a pnp bipolar transistor can be used if diode connected to act as a bootstrap diode, getting a voltage loss of around the base emitter on voltage =~ 0.8 V or more (depending on the technology). In this situation if the charging (PVCC) voltage is 5 V, the bootstrap capacitor can reach only 4.2 V (or less) over the lower supply voltage (PHASE level, in this case). This means that the maximum internal supply voltage can be 4.2 V; but if we consider ripple and spikes this could be even lower. The circuit behavior could be worsened.

With the use of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), it is possible to decrease the voltage loss as the VDS,sat of a MOSFET is lower than a VBE,on of a bipolar, especially when overdrive is sufficiently high. If VDS is around 0.2-0.3 V, an increase in the voltage headroom is obtained available of 0.5 V.

The core of the idea is the use of parallel high voltage PMOS (Positive Channel Metal Oxide Semiconductor) in such a way that they conduct only in one direction i.e. they must be turned off when PWM (Pulse Width Modulation) (and consequently high side gate and phase) rise up. In such a way the PMOS can charge the bootstrap capacitor to the PVCC voltage during the period in which PWM is low. A signal is needed to turn on the PMOS, and it has to be latched in the on condition till the reset pulse is given by the PWM signal going low.

In one o...