Browse Prior Art Database

Method to Flip Chip Stacking

IP.com Disclosure Number: IPCOM000130308D
Published in the IP.com Journal: Volume 5 Issue 11A (2005-11-25)
Included in the Prior Art Database: 2005-Nov-25
Document File: 2 page(s) / 435K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

In the current assembly process of stacked FBGA (Fine Pitch Ball Grid Array) packages with identical or similar die sizes, it is necessary to use an interposer or spacer between both chips in order to protect the bond wires of the mother die (bottom chip). The interposer is normally a piece of Silicon, which are attached at die level between the mother die (bottom) and the daughter die (top) during the stacked FBGA assembly process. The current solution is based on a die-level process, which means a serial and cost intensive and time consuming process (see Fig. 1).

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Method to Flip Chip Stacking

Idea: Bernd Zimmermann, DE-Dresden; Stefan Ruckmich, DE-Dresden

In the current assembly process of stacked FBGA (Fine Pitch Ball Grid Array) packages with identical or similar die sizes, it is necessary to use an interposer or spacer between both chips in order to protect the bond wires of the mother die (bottom chip).

The interposer is normally a piece of Silicon, which are attached at die level between the mother die (bottom) and the daughter die (top) during the stacked FBGA assembly process. The current solution is based on a die-level process, which means a serial and cost intensive and time consuming process (see Fig. 1).

The main idea is to use the Infineon ELASTec-bump or conventional solder balls and RDL (Redistribution Layer) technology for stacking dies using Flip Chip Technology and the possibility to off center dies inside the package combined with a new substrate design.

The benefits of this solution are a process simplification because there are no additional spacer attach process at die-level necessary, no wire bonding process necessary and there is an improvement of die attach process stability. Furthermore, the package reliability increases. There is more effective area of adhesion between mold compound and chips in package. The solution saves costs because of savings of Silicon-Spacer and glue material, and of savings of wire bond material and process. In addition, there is a larger throughput due to a simplified...