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Method for a filling process to form CMOS ICs

IP.com Disclosure Number: IPCOM000130418D
Publication Date: 2005-Oct-24
Document File: 8 page(s) / 233K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a filling process to form complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Benefits include improved functionality and improved performance.

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Method for a filling process to form CMOS ICs

Disclosed is a method for a filling process to form complementary metal oxide semiconductor (CMOS) integrated circuits (ICs). Benefits include improved functionality and improved performance.

Background

      Metal gate electrode fill can occur in dual-metal (damascene) replacement gate process flows created with high aspect ratio and reentrant profiles. Conventional solutions result in marginal filling or are not fully developed.

              Conventional manufacturing techniques use subtractive poly-silicon (poly-Si) gates on nitrided gate oxides. One solution is poly-Si gate patterning with a tip implant (see Figure 1).

      Another solution includes the following items (see Figure 2):

•             Poly-Si gate sidewall space

•             Source/drain implants

•             Silicide deposition

•             Salicide formation

General description

              The disclosed method is a force-fill approach to achieve metal gate electrodes for high aspect ratio and reentrant profiles for replacement gates with high dielectric constant (high-k) dielectric materials/layers. One example of a force-fill approach used previously for Al and Au interconnect formation has been demonstrated by Trikon Technologies.

              A key element of the disclosed method is the utilization of a diffusional flow of metal gate fill material to enable replacement gate electrode filling of high-k dielectric gates.

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing an integrated solution where metal gates are used to avoid a poly-depletion effect
•             Improved performance due to preventing a poly-depletion effect that degrades transistor device performance

 •            Improved performance due to being fully compatible with high-k gate dielectrics

•             Improved performance due to eliminating voids and adverse structural seams

Detailed description

      The disclosed method eliminates adverse metal seams and voiding for high aspect ratio or reentrant profiles in dual-metal (damascene) replacement gate processes. Metal gates are filled using sputter deposition, chemical vapor deposition (CVD), or atomic layer deposition (ALD) of fill materials, including aluminum (Al), copper (Cu), and silver (Ag). The wafer is heated and subjected to mechanical pressure to reflow the material. When Al is used, titanium (Ti) is used as a wetting layer. Al is used in applications with minimal thermal impact. Cu requires more robust wetting agents, such as the following:

•             Oxidized tantalum (Ta) or TaN

•             Metallic Ta

•             Cobalt (Co)

•             Nickel (Ni)

•             Ruthenium (Ru)

      Restrictions on gate feature sizes are controlled by design rule limits to prevent voids between gates and wider features.

              A...