Browse Prior Art Database

Method for interconnecting underlying CMOS circuits to a gold damascene layer

IP.com Disclosure Number: IPCOM000130471D
Publication Date: 2005-Oct-25
Document File: 6 page(s) / 398K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for interconnecting underlying complementary metal oxide semiconductor (CMOS) circuits to a gold (Au) damascene layer. Benefits include improved functionality and improved performance.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Method for interconnecting underlying CMOS circuits to a gold damascene layer

Disclosed is a method for interconnecting underlying complementary metal oxide semiconductor (CMOS) circuits to a gold (Au) damascene layer. Benefits include improved functionality and improved performance.

Background

              Conventionally, Au electrode patterning at a submicron dimension for a ferroelectric polymer memory device is not available. Gold is very difficult to etch to submicron geometries. Most processes that utilize patterned Au rely on wet etches or lift off processes. Attempts to perform submicron Au patterning have failed due to uniformity and defect issues. The state of the art for evaluating Au electrodes on ferroelectric polymer memory is a test capacitor with dimensions of millimeters (see Figure 1).

General description

              The disclosed method is a process to create submicron interconnections of noble metals, such as gold, to underlying CMOS circuits without a subtractive etching process. For example, a gold damascene layer interconnects to tungsten (W) plugs connecting to the underlying CMOS. The disclosed method is useful for any process, such as ferroelectric polymer memory, that requires a gold or other noble metal connection to CMOS circuits.

              The disclosed method eliminates the requirement for gold etching and creates a successful connection to the underlying CMOS layer.

              The key elements of the disclosed method include:

•             Termination of the CMOS layer with a via fill material layer, such as an oxide interlayer dielectric (ILD) layer, that has tungsten plugs available for interconnection

•             Etching of a damascene trench using a deposited oxide, nitride, or polymer, so that the tungsten plug is exposed

•             Creation of a gold-filled trench

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to providing the interconnection of submicron noble metal materials, such as gold, to underlying CMOS circuits without a subtractive etching process
•             Improved performance due to providing good gapfill

•             Improved performance due to providing successful adhesion to the film in which the trench was etched and the tungsten plug itself

•             Improved performance due to providing successful electrical contact between the tungsten plug and the metal(s) in the damascene trench

Detailed description

              The disclosed method interconnects an active CMOS device to a metal layer that contains the tops of tungsten plugs (see Figure 2).

              Chemical vapor ...