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Method for stacked capacitors for package real estate savings and loop inductance improvement

IP.com Disclosure Number: IPCOM000130479D
Publication Date: 2005-Oct-25
Document File: 4 page(s) / 38K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for stacked capacitors for package real estate savings and loop inductance improvement. Benefits include improved functionality and improved performance.

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Method for stacked capacitors for package real estate savings and loop inductance improvement

Disclosed is a method for stacked capacitors for package real estate savings and loop inductance improvement. Benefits include improved functionality and improved performance.

Background

      To reduce the inductive effect of the electrical traces, several capacitors are connected in parallel to meet the required capacitance. These capacitors are placed laterally to each other on a package. As the requirement for the number of packages increases with each generation of new products, more capacitors are required to be placed on the package.

      Conventionally, a capacitor is placed on the package die side. Two capacitors are placed in the lateral plane of the surface layer and are connected to the same power (VCC) and ground (VSS) plane of the package. Both of the capacitors provide power to the package die. The capacitors are connected to create a parallel circuit. Each capacitor contributes a different loop inductance, which depends on the distance from the die. The further the capacitor is placed from the die, the bigger the loop inductance (see Figures 1 and 2).

      Based on a model of the conventional capacitor placement of approximately 3.8-mm from the die, loop L results in 556 pH. Placement of a second capacitor 5.62-mm from the die, loop L results in 767 pH. The total parallel loop L between these 2 capacitors is 322 pH. The resultant loop inductance for the capacitor stackup is halved due to the parallel connection between the two capacitors. As more capacitors are stacked, loop L is increasingly reduced.                        

      Space constraints limit the number of capacitors that can be included in a package. Future products are expected to require an increased number of decoupling solutions for dice that require an increasing amount of power. With a shrinking package size for optimum signal integrity performance, the conventional decoupling solutions present a major problem and may become a limitation for the development of the next generation packaging technology.

      As a result, the component keep out zone (KOZ) is reduced so that more capacitors can be included in a package. This innovation is limited by the manufacturing capability to reduce the KOZ and its epoxy underfill.

General description

      The disclosed metho...