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Automatic Removal of Connector Errors from Board Manufacturing Tests

IP.com Disclosure Number: IPCOM000130523D
Publication Date: 2005-Oct-25
Document File: 2 page(s) / 27K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a automated method for detecting and correcting connector errors at functional test stations on manufacturing lines.

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Automatic Removal of Connector Errors from Board Manufacturing Tests

Disclosed is a automated method for detecting and correcting connector errors at functional test stations on manufacturing lines.

Background

Currently, cable and connector wear and bad connections cause many false failures during board functional tests; this leads to lower beat rates and an increase in the number of boards being reworked unnecessarily.

All connector tests are run randomly throughout the test process; this means that some may be tested for functionality without first being presence-tested. This can waste a lot of time, and create situations where an operator may know not know exactly what to do when a failure occurs.

General Description

The disclosed method breaks the “board functional test” step of motherboard testing into two distinct phases: the connector and cable testing, and the functional testing. 

In the first phase, the only tests executed are for detecting and verifying the presence of cables and cards. All of the gold hardware required for the test to work is tested for. This means that each piece that plugs into the unit under test (UUT) is tested for being present without being tested for functionality. If anything in this phase fails, the operator is given the option of fixing the error without causing a failure to the shop floor control system (SFCS), which allows for a greater beat rate on the line (i.e. rate of board production). When a board fails in SFCS, it must go b...