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Using Assertion Based HDL Simulation to estimate the fault coverage of memory tests

IP.com Disclosure Number: IPCOM000130725D
Published in the IP.com Journal: Volume 5 Issue 11B (2005-12-10)
Included in the Prior Art Database: 2005-Dec-10
Document File: 3 page(s) / 64K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

Semiconductor memories are subject to malfunctions caused by faults. It is difficult to detect all faults in a semiconductor memory. In order to minimize testing and production costs, production tests are tailored for detecting faults which will occur with high probability in a given circuit design or manufacturing process. Unexpected failing mechanisms may cause yield losses. Faults not detected during production tests may lead to customer returns. Recovering the faults may take long turnaround times in case a redesign of the memory is necessary. Also changes in the testing methodology may not be possible without modifying the device circuitry. At present, if unexpected faults are discovered or lots of devices are returned by customers due to malfunction, one or more among the following actions is taken: - review the memory circuit design - adjust the manufacturing process - adapt the test sequence to changed fault distributions. These recovery actions are taken in reaction to problems detected at late stages. The later the stage at which the problem occurs, the higher is the impact on costs and revenues. In those cases where the problem can be recovered by increasing the fault coverage of the memory tests, improving the test sequence usually leads to significant longer testing times. This also impacts production costs.

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Using Assertion Based HDL Simulation to estimate the fault coverage of memory tests

Idea: Mario Di Ronza, DE-Munich

Semiconductor memories are subject to malfunctions caused by faults. It is difficult to detect all faults in a semiconductor memory. In order to minimize testing and production costs, production tests are tailored for detecting faults which will occur with high probability in a given circuit design or manufacturing process. Unexpected failing mechanisms may cause yield losses. Faults not detected during production tests may lead to customer returns. Recovering the faults may take long turnaround times in case a redesign of the memory is necessary. Also changes in the testing methodology may not be possible without modifying the device circuitry.

At present, if unexpected faults are discovered or lots of devices are returned by customers due to malfunction, one or more among the following actions is taken:

- review the memory circuit design

- adjust the manufacturing process

- adapt the test sequence to changed fault distributions.

These recovery actions are taken in reaction to problems detected at late stages. The later the stage at which the problem occurs, the higher is the impact on costs and revenues. In those cases where the problem can be recovered by increasing the fault coverage of the memory tests, improving the test sequence usually leads to significant longer testing times. This also impacts production costs.

The suggested idea is to simulate faults in the memory model digitally in order to estimate the fault coverage as well as the cost of memory tests. This can be realized by measuring the amount of faults detected by means of assertions. Within hardware description language (HDL) designs, an assertion is a conditional statement that checks for expected or unwanted system behavior and displays a message if it occurs. Faults are injected in the memory model according to types and distribution defined in a list of fault descriptors. Basing on fault descriptors, an assertion compiler automatically extracts a corresponding set of assertions to check the expected behavior of the memory tests in reaction to the predefined faults. The verification flow is based on digital simulations of the memory and the infrastructure which generates the test patterns.

Compared to analog simulations in which only small memory sub-circuits are verified to keep the runtime reasonably short, digital simulation allows checking the behavior of a model representation of the entire memory. Memory models can be either behavioral, cycle accurate or timing accurate; the more detailed the modeling, the more realistic the digital simulation at the cost of longer simulation runtimes. During simulation, an assertion based language simulator generates an assertions coverage report. By examining the report, it is possible to estimate the fault coverage and the efficiency of the tests applied.

The assertion-based verification flow for memo...