Browse Prior Art Database

Program Counter Register Design in a Microcontroller to increase the Throughput

IP.com Disclosure Number: IPCOM000131059D
Published in the IP.com Journal: Volume 5 Issue 11B (2005-12-10)
Included in the Prior Art Database: 2005-Dec-10
Document File: 2 page(s) / 62K

Publishing Venue

Siemens

Related People

Juergen Carstens: CONTACT

Abstract

At present, a low jitter clock circuit is designed to ensure fast processing speed of all received data and firmware instructions. Though, this depends on a low phase noise, high frequency and power matching network of the external/internal clock. In the following paragraphs a further solution is proposed. It can be expected that the processing speed is getting slower the more cycles each instruction within the microcontroller takes. For example, microcontroller instructions which are implementing a variety of branching or call and return operations take a minimum of two cycles – one for fetching and one for executing the instruction. The conventional program counter keeps track of the address of the next instruction to be executed, and the CPU begins each instruction cycle by fetching the first byte of the next instruction and automatically incrementing the program counter. Based on the operation code byte the CPU recognizes whether it needs more bytes to complete the fetching of a multiple-byte instruction. After fetching as many bytes as called for, the present instruction has been completed and the program counter will be ready to get the next instruction.

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Program Counter Register Design in a Microcontroller to increase the Throughput

Idea: Jin Sze Sow, SG-Singapore

A good performance of network processing, routing, electronic devices, etc. requires

- fast interactions between a microcontroller and external hardware and/or

- a fast controller architecture.

At present, a low jitter clock circuit is designed to ensure fast processing speed of all received data and firmware instructions. Though, this depends on a low phase noise, high frequency and power matching network of the external/internal clock.

In the following paragraphs a further solution is proposed. It can be expected that the processing speed is getting slower the more cycles each instruction within the microcontroller takes. For example, microcontroller instructions which are implementing a variety of branching or call and return operations take a minimum of two cycles - one for fetching and one for executing the instruction. The conventional program counter keeps track of the address of the next instruction to be executed, and the CPU begins each instruction cycle by fetching the first byte of the next instruction and automatically incrementing the program counter. Based on the operation code byte the CPU recognizes whether it needs more bytes to complete the fetching of a multiple-byte instruction. After fetching as many bytes as called for, the present instruction has been completed and the program counter will be ready to get the next instruction.

The core of the proposed idea is to use multiple program counters to keep track of the subsequent instruction addresses. At any one time, a single read enabled program counter will be providing the instruction address to the program memory and one (or more) write enabled program counter(s) will "pop" the address starting from the top of the stack. The read enabled program counter will proceed to become a write enabled program counter and "pop" the...