Browse Prior Art Database

IEEE Computer Volume 11 Number 1 -- REPOSITORY

IP.com Disclosure Number: IPCOM000131229D
Original Publication Date: 1978-Jan-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 4 page(s) / 20K

Publishing Venue

Software Patent Institute

Related People

IEEE Computer Society: OWNER [+2]

Abstract

REPOSITORY * R78-1 -- Kim, Kwang Hae, ";Optimizing Architectures in Parallel Processing"; * R78-2 -- Smith, James E., ";Detection of Faults in Programmable Logic Arrays"; * R78-3 -- Baugh, C.R., and B.A. Wooley, ";A High.Speed, Low.Power Bipolar, One. Bit Full Adder"; * R784 -- Ghosh, Sukumar, ";Structured Petri Nets"; * R78-5 -- Galkowski, J.T., ";Language Reference Manual for RED/i: A Red Language for Variable.Free Programming"; * R78-6 -- Varshney, Pramod K., ";Intermittent Faults in Digital Systems: Analytical Models"; * R78-7 -- Oliver, B.M., and R. F. Eschenbach, ";An Algorithm for Efficient Coordinate Rotation * R78-8 -- Parhami, Behrooz, and Kaykhosrow Alvandi, ";A Minicomputer-Based Direct Numerical Control System"; * R78-9 -- Zaks, S., ";Generating Binary Trees Lexicographically"; * R78-10 -- Tietz, Leon Clemens, ";Burst. logic: Design and Analysis of Logic to Perform Arithmetic on Data in the Burst Format";

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

REPOSITORY

a collection of over 2600 technical papers (some refereed some not) covering the full range of - :computer system design and maintained by the Computer Society as a service to the information nrnrQccinn r.nmmunitv

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R78-1 -- Kim, Kwang Hae, "Optimizing Architectures in Parallel Processing"

(268 pp., University of California, Berkeley, California)

This paper investigates optimization aspects in designing and operating a parallel processing system of super computing power. Specific subjects studied or results obtained include practical tools for parallelism indication, technical foundation for detecting useful parallelism hidden in parallel programs, a modular architecture for effective parallelism utilization, optimization techniques relevant to machine design, static sequencing and static storage allocation, cost- effective validation of parallel programs, and a scheme for concealing run-time overhead incurred in dynamic optimization.

R78-2 -- Smith, James E., "Detection of Faults in Programmable Logic Arrays"

(25 pp. University of Wisconsin, Madison, Wisconsinl

A new fault model is proposed for the purpose of testing programmable logic arrays. It is shown that a test set for all detectable modeled faults detects a wide variety of other faults. A test generation method for single faults is then outlined. Included is a bound on the size of test sets which indicates that test sets are much smaller than would be required...