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IEEE Computer Volume 11 Number 9 -- New Products

IP.com Disclosure Number: IPCOM000131238D
Original Publication Date: 1978-Sep-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 5 page(s) / 24K

Publishing Venue

Software Patent Institute

Related People

D. A. Michalopoulos: AUTHOR [+3]

Abstract

New Products

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

New Products

edited by

Prof. D. A. Michalopoulos
California State University, Fullerton edited by
Prof. D. A. Michalopoulos California State University, Fullerton

Quarter-million-bit magnetic bubble memory announced by Tl

Sample quantities of a new quartermillion bit magnetic bubble memory priced at $500 each win be available in the fourth quarter of 1978, Texas Instrumerits has announced. The company also said its 92K-bit bubble memory is now in volume production and available six weeks after receipt of order at $100 in 100-piece quantities. Interface and con trol circuits for the 92K device are currently available, as well, TI said.

Designated the TIB0303, the quartermiUion-bit device with 3- micron-diameter magnetic bubble domains uses separate I/O, minor loop architecture featuring block replication of data, and separate read and write tracks with minor loop data storage.

A total of 252 minor loops, each consisting of 1137 bubble positions, results in a single-chip memory capacity of 286,524 bits. However, 224 loops are utilized resulting in a maximum data capacity of 254,688 bits.

Data bits are written into the write track and exchanged with stored data in the minor loops via swap gates. Data blocks are replicated simultaneously at minor loop and output track junctions, rather than serial duplication which is characteristic of major/minor loop architecture. Consequently, power-down cycle time is significantly reduced from 12.8 msec in the 92K-bit major/minor loop configuration to 12.5 psec for block replicate, representing three orders of magnitude improvement, TI states.

Other key features include asymmetric chevron design for improved bubble propagation and transfer, merged data that allows a continuous flow of data bits at the read track, and a dedicated loop for storage of on-chip redundancy information and address synchronization.

Performance specifications at 100-kHz operation are an average access time of 7.3 msec for the first bit of the 224-bit page and a typical power consumption of 0.9 W for continuous operation. A data-merge function allows a read data rate of 100K bits per second. Operating temperature is 0 to 50 C with nonvolatile storage range of -- 40 to 85 C.

Bubble control functions such as generate, swap, block replicate and redundancy replicate are executed by providing current pulses through the appropriate control elements on the chip.

The bubble chip is composed of a gadolinium-gallium garnet substrate upon which a magnetic epitaxial film is grown. Patterns of permalloy metal are depos...