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High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing

IP.com Disclosure Number: IPCOM000131245D
Original Publication Date: 1978-Oct-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 11 page(s) / 42K

Publishing Venue

Software Patent Institute

Related People

Shlomo Waser: AUTHOR [+3]

Abstract

Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.

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This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

High-Speed Monolithic Multipliers for Real-Time Digital Signal Processing

Shlomo Waser

Monolithic Memories, Inc.

Real-time digital signal processing requires very fast multiplication, which is now becoming possible using mathematical techniques to take advantage of single-chip multipliers.

In the past, most digital signal processing has required that digitized signals be recorded and then processed off- line on general-purpose computers. In many cases, however, on-line, real- time, and therefore very fast processing is required if digital techniques are to successfully replace analog techniques. The ultimate limitation on speed, and hence filter or spectrum- analyzer bandwidth, is multiplication speed. It has recently become feasible to implement fast multipliers on single silicon chips, and these monolithic devices promise to make real-time digital signal processing widely available.

In digital signal processing, a sampled point of the analyzed waveform may require one addition and one multiplication. The multiplication is traditionally performed by successive addition, so that for e-bit data words, n additions are required. For example, if the analog signal is quantized into eight bits, the required computation is made of nine additions -- one for the real addition and eight simulating a multiplication. If the multiplication speed were to match the addition speed, the bandwidth of the signal processor would increase by a factor of four. For 16-bit words, a matching multiplication speed would improve the bandwidth by a factor of eight.

Simple multiplication: add and shift

The add-and- shift algorithm is the simplest way to perform a multiplication when only adding and shifting resources are available. The principle is similar to the way one multiplies numbers using pencil and paper. For example, multiplying two unsigned binary numbers is done as follows:

6.....110
5 .....101
6X..... 110
OX2'..... 000
6X2Z.....110
30.....11110

When this operation is simulated in a software routine, each bit of the multiplier results in one add and one shift operation. Since most computers can add and shift in the same instruction cycle, at least n operations are required for n bits of multiplication. Figure 1 illustrates the MSI implementation of a sequential multiplier made up of an adder and a shift register. This sequential method is adequate for lowspeed multiplication; for high-speed multiplication a combinatorial approach is needed.

In a combinatorial approach, the partial products are formed simultaneously and then added ...