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PROPOSED STANDARD FOR THE S-100 BUS Disclosure Number: IPCOM000131310D
Original Publication Date: 1978-May-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 9 page(s) / 33K

Publishing Venue

Software Patent Institute

Related People

George Morrow: AUTHOR [+4]


, Parasitic Engineering, Inc.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 12% of the total text.

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This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.


George Morrow , Thinker Toys Howard Fullmer , Parasitic Engineering, Inc.

Members, IEEE Computer Society Microprocessor Standards Committee

The computer bus commonly known as the S-100 was first introduced by MITS, Inc., with its Altair kit. This bus has since spread throughout the electronics industry and beyond. Today over a hundred manufacturers make products which claim to be compatible with the S-100 bus even though -- until now -- no complete specification has been available. The following table, figures, and notes constitute the preliminary draft of a proposed standard for the S-100 bus.

This document is a specification for both timing and signal disciplines. Signal discipline is described using the bus master/bus slave language long associated with Digital Equipment Corporation's PDP-11. This point of view facilitated the deyelopment of a simple and highly reliable DMA protocol, the extended addressing capabilities, and the 16-bit wide data path proposals. These extensions to the original Altair bus represent a significant advance to the state of the art of small computers and are a direct result of a continuing dialogue with a large number of interested people who have contributed their thoughts and ideas to the standards committee. The extended address and data proposals are compatible with systems that don't use these features, including most existing systems. Signals which are defined or redefined for the extensions are indicated by an asterisk.

    (Image Omitted: S-100 Bus Signal Definitions (preliminary -- subject to revision) .....PIN
NO......SIGNAL NAME & TYPE.....POLARITY.....DESCRIPTION 1.....+8 volts (B)'Instantaneous
minimum greater than 7 volts, instantaneous maximum less than 25 volts, average maximum less than 11 volts. 2.....+ 16 volts (B)Instantaneous minimum greater than 14 volts,
instantaneous maximum less than 35 volts, average maximum less than 20 volts. 3.....XRDY
(S)' ' .....positive.....One of two ready inputs to the current bus master. The bus is ready when
both these ready inputs are true. 4.....VlO (S)' .....negative.....Vectored interrupt line 0. 5.....Vl1
(S)' .....negative.....Vectored interrupt line 1. 6.....Vl2 (S)' .....negative.....Vectored interrupt line 2.
7.....Vl3 (S)' .....negative.....Vectored interrupt line 3. 8.....Vl4 (S)' .....negative.....Vectored
interrupt line 4. 9.....Vl5 (S)' .....negative.....Vectored interrupt line 5. 10.....Vl6 (S)'
.....negative.....Vectored interrupt line 6. 11.....Vl7 (S)' .....negative.....Vectored interru...