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The Intel 6086 Microprocessor: A 16-bit:: Evolution of the 8060

IP.com Disclosure Number: IPCOM000131318D
Original Publication Date: 1978-Jun-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 14 page(s) / 47K

Publishing Venue

Software Patent Institute

Related People

Stephen P. Morse: AUTHOR [+5]

Abstract

The architecture and instruction set of this new 16-bit microprocessor were designed to meet the requirements of a broad spectrum of new microprocessor applications. The new Intel 8086 microprocessor was designed to be a compatible successor to the 8080, and yet it provides an order of magnitude increase in processing throughput over the older machine. The processor design was constrained to be assembly-language-level compatible with the 8080 so that existing 8080 software could be reassembled and correctly executed on the 8086. To allow this compatibility the 8080 register set and instruction set have to appear as logical subsets of the 8086 registers and instructions. The goals of the 8086 architectural design were to provide symmetric extensions of existing 8080 features, as well as the following new processing capabilities not found in the 8080: 16-bit arithmetic, signed 8- and 16-bit arithmetic (including multiply and divide), efficient interruptible byte-string operations, improved bitmanipulation facilities, mechanisms to provide for re-entrant code, position- independent code, dynamically relocatable programs. Another design goal was to be able to address directly more than 64K bytes and support multiprocessor con figuration s 2

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

The Intel 6086 Microprocessor: A 16-bit:: Evolution of the 8060

Stephen P. Morse

William B. Pohlman

Bruce W. Ravenel

Intel Corporation

The architecture and instruction set of this new 16-bit microprocessor were designed to meet the requirements of a broad spectrum of new microprocessor applications.

The new Intel 8086 microprocessor was designed to be a compatible successor to the 8080, and yet it provides an order of magnitude increase in processing throughput over the older machine. The processor design was constrained to be assembly-language-level compatible with the 8080 so that existing 8080 software could be reassembled and correctly executed on the 8086. To allow this compatibility the 8080 register set and instruction set have to appear as logical subsets of the 8086 registers and instructions.

The goals of the 8086 architectural design were to provide symmetric extensions of existing 8080 features, as well as the following new processing capabilities not found in the 8080: 16-bit arithmetic, signed 8- and 16-bit arithmetic (including multiply and divide), efficient interruptible byte-string operations, improved bitmanipulation facilities, mechanisms to provide for re-entrant code, position- independent code, dynamically relocatable programs. Another design goal was to be able to address directly more than 64K bytes and support multiprocessor con figuration s 2

The 8086 memory structure includes up to one megabyte of memory space and up to 64K bytes of input/output ports. The register structure includes three files of registers. Four 16-bit general registers can participate interchangeably in arithmetic and logic operations, two 16-bit pointer and two 16-bit index registers are used for address calculations, and four 16-bit segment registers allow extended addressing capabilities. Nine flags record the processor state and control its operation.

The instruction set supports a wide range of addressing modes and operations for data transfer, signed and unsigned 8- and 16-bit arithmetics, logicals, string manipulation, control transfer, and processor control. The external interface includes a reset sequence, interrupts, and a multiprocessor-synchronization and resource-sharing facility.

(Image Omitted: Intel 8086 Device Characteristics .....ALU Width:.....16 bits Memory addressing
capability:.....1,048,576 bytes Addressable l/O ports:.....64K Process:.....HMOS Gate
propagation delay:.....~ 2 ns Clock period: 200 ns standard.....125 ns selected Memory access:
800 ns standard.....500 as selected Relative performa...