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Mainframe Implementation With Off-The-Shelf LS' Modules

IP.com Disclosure Number: IPCOM000131330D
Original Publication Date: 1978-Jul-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 10 page(s) / 38K

Publishing Venue

Software Patent Institute

Related People

Barry R. Borgerson: AUTHOR [+5]

Abstract

[Figure containing following caption omitted: Bit-sliced microprocessor parallel design for Sperry Univac 1108 improves performance, reduces build cost, and detects most faults.] Applying LSI technology to the processors of mainframe computer systems has been difficult because of the relative randomness of the logic involved in implementing the processor function. Several approaches for solving this problem of matching technology to function have been proposed or used:

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1978 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Mainframe Implementation With Off-The-Shelf LS' Modules

Barry R. Borgerson . Garold S. Tjaden , and Merlin L. Hanson

SDerrv Univac

(Image Omitted: Bit-sliced microprocessor parallel design for Sperry Univac 1108 improves performance, reduces build cost, and detects most faults.)

Applying LSI technology to the processors of mainframe computer systems has been difficult because of the relative randomness of the logic involved in implementing the processor function. Several approaches for solving this problem of matching technology to function have been proposed or used:

Custom LSI. In this approach the logic design of the processor is mapped into a set of unique LSI chips. However, problems in partitioning the logic design to meet the gate- density and pin constraints of the LSI chips are significant. Given current levels of integration for high- performance technologies (transistor-transistor logic and emittercoupled logicI, a large number of custom chip types would be necessary to implement a mainframe processor. Because of the relatively low volume of usage of these chips, this approach has been too expensive.

Gate array.

This approach is employed in the Amdahl 470/V6 computer.' A gate array is an LSI chip having an array of gates fabricated on it in a regular pattern. These chips are used to implement specific logic functions by customizing the metal interconnections between gates. Gate- array chips are less expensive than totally customized LSI chips because all of the processing steps except the ones of metallization are common. However, gate speed and density are sacrificed because it is not always possible to optimize for specific functions.

LSI modular.

For this approach a small set of LSI chip types (ideally one) is defined so that a Processor having mainframe-equivalent performance

can be constructed by suitably interconnecting a number of these chips. Existing bit-sliced chip sets such as the Motorola M10800 and AMD 2900 are examples of LSI modules which can be used in this approach. Definition of a single LSI chip type (module) suitable for this approach has not yet been achieved, but interesting research results have been reported.2-5 Low cost due to high volume usage of a small number of chip types is the potential payoff of this approach.

New design technique.

This article presents and evaluates new design techniques for achieving mainframe performance with the LSI modular approach utilizing off-the- shelf modules. Evaluation data

IEEE Computer Society, Jul 01, 1978 Page 1 IEEE Computer Volume 11 N...