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Charge-Coupled Device Memories: A Perspective Disclosure Number: IPCOM000131365D
Original Publication Date: 1979-Jan-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 9 page(s) / 36K

Publishing Venue

Software Patent Institute

Related People

D.P. Bhandarkar: AUTHOR [+5]


Texas Instruments, Inc.

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This record contains textual material that is copyright ©; 1979 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Charge-Coupled Device Memories: A Perspective

D.P. Bhandarkar Digital Equipment Corp.

J.B. Barton , A.F. Tasch, Jr. Texas Instruments, Inc.

COD memories can fill the gap between RAMs and disks. If cost-effective, they will tend to be used in high-end, high- performance computers.

Semiconductor memory technology has progressed rapidly since the first devices became available in 1968. Today, semiconductors have replaced core as the preferred mainframe memory. The charge-coupled device, a variant of a metal-oxide semiconductor, was introduced in 1970 and is em- ployed today in a wide variety of applications in signal processing, memory, and imaging. CCD memories were initially designed as shift registers or block-oriented RAMs, although the concept of charge-coupling has been applied to all types of RAMs.' For our purposes, CCD means a chargecoupled shift register.

Although the CCD is a relatively new application of semiconductor technology, the CCD fabrication process is very similar to the standard silicon-gate process used to build e-channel dynamic MOS RAMs. New CCD structures also allow the cost-effective implementation of shift- register storages CCDs are intended to fill the performance gap between highspeed RAMs and magnetic disks (see Figure 1). In addition to having shorter access times than disks, CCDs allow users and designers to take a modular approach to storage, where the price per bit is insensitive to capacity. This allows a user to start with a lowcapacity system, at a low entry cost, and expand capacity in modular increments. With today's devices, the modular increments will be in the 1M-4M bit range at the circuit-board level; for small systems, the modular increment can be 16K-64K bits at the chip level.

CCDs in a memory hierarchy

The objective of using a memory hierarchy is to provide the central processor with an apparent highspeed, large-capacity memory system at a minimum cost. Since the information in a memory system is unlikely to be accessed all at once, memory-management algorithms are employed to keep related subsets of information in high-speed RAM storage while the rest of the information resides in lower levels of the storage hierarchy. The system designer must select the number of levels in the hierarchy and the storage capacity at each level.

(Image Omitted: Figure 1. Memory technology: cosVperiormance protections for 1980.)

Figure 2 shows two alternative memory hierarchies. On the right, a fast auxiliary memory is inserted between the RAM and the mass storage. Since this is cost e...