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VLSI Architecture, Design, and Fabrication Disclosure Number: IPCOM000131397D
Original Publication Date: 1979-May-01
Included in the Prior Art Database: 2005-Nov-10
Document File: 5 page(s) / 27K

Publishing Venue

Software Patent Institute

Related People

Philip M. Neches: AUTHOR [+3]


California Institute of Technology

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This record contains textual material that is copyright ©; 1979 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

VLSI Architecture, Design, and Fabrication

Philip M. Neches

California Institute of Technology

100 million devices per chip? 50 picosecond gate transit times? As technology marches toward the realization of such heady projections, researchers are addressing the design challenges inherent in such complexity.

What would I do with 106 transistors on a chip?" With that question Intel Board Chairman Gordon Moore set the tone in his keynote address to nearly 500 conference registrants from industry, academia, and government. During the three days from January 22 to 24, 1979, invited speakers, refereed papers, and panel discussions dealt with various aspects of that theme.

The conference, titled "Very Large Scale Integration: Architecture, Design, and Fabrication," was held on the Caltech campus in Pasadena under the sponsorship of the Computer Science Department and the Industrial Associates Office.

In the first invited talk, Ed Wolf of Cornell discussed the goals of the National Sub-Micron Facility. Besides the obvious payoff for integrated circuits, advancing sub-micron fabrication technology will open up new areas, including new archival memories, and such non-computer applications as fabrication of transducers of biological scale and research into phenomena which occur at extreme pressure (106 bar). Wolf spoke of submicron fabrication as the means to maintain "an unassailable U.S.A. position in microelectronics and computer science."

Professor Wolf then turned to lithe ographic techniques and their anticipated theoretical limits of resolution. Visible and ultraviolet light techniques have not yet been pushed to their limits, he claimed, with perhaps 0.2pm as the ultimate end point. Electron beam techniques are believed capable of achieving 0.11lm resolution. X-ray techniques appear to have a theoretical limit of 50i, which could be equaled (although this is by no means certain) by focused ion beam technology, the latter a relative newcomer.

The next invited speaker, Amr Mohsen of Intel Corporation, then took to the podium with some controversial and heady projections for VLSI devices and circuits in the 1990-2000 time frame. Dr. Mohsen envisioned chips with 100 million devices (as opposed to today's 100 thousand). These chips would be fabricated with 0.2-pm minimum feature sizes (versus 2pm today), operate on 0.5V power supplies /versus 5V today), have gate transit times of 50 picoseconds (versus 1 nanosecond today), and speed-power products of 2 femtojoules (versus 10 to 1000 picojoules today). Dr. Mohsen predicte...