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Standard Specification for S-100 Bus Interface Devices

IP.com Disclosure Number: IPCOM000131415D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Nov-10

Publishing Venue

Software Patent Institute

Related People

Kells A. Elmquist: AUTHOR [+5]

Abstract

, Stanford Linear Accelerator Center George Morrow , Thinker Toys This proposed standard eliminates many of the problems in the S-100 bus and upgrades it for 16-bit microprocessors. It is offered here for public comment before submission to the IEEE Standards Board.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 5% of the total text.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1979 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Standard Specification for S-100 Bus Interface Devices

IEEE Task 696.1/ D2

Kells A. Elmquist , InterSystems Inc.

Howard Fullmer , Parasitic Engineering Inc.

David B. Gustavson , Stanford Linear Accelerator Center

George Morrow , Thinker Toys

This proposed standard eliminates many of the problems in the S-100 bus and upgrades it for 16-bit microprocessors. It is offered here for public comment before submission to the IEEE Standards Board.

Introductory comments by Robert G. Stewart, Chairman, IEEE-CS Computer Standards Committee

The following draft of a proposed standard for the S-100 bus is the culmination of over a year and a half of effort to eliminate many of the bus's problems and to upgrade it to be suitable for 16-bit microprocessors. The address bus has been extended to 24 bits, the data in and data out buses ganged to form a 16-bit wide data bus for 16-bit transactions, and two additional handshaking lines added to permit intermixing of 8- and 16-bit memory cards.

A binary encoded multiple master arbitration bus permits up to 16 masters on the bus. The necessary logic can be implemented in one chip. Additional ground lines, a power fail line, and an error line have been added. Three lines termed NDEF -- for not to be defined -- have been allotted to allow leeway to implementers for specialized use. Such use must be specified in all literature. Five lines are RFU -- reserved for future use. Some lines formerly used for front panel purposes have been deleted, with the intention that such lines can best be handled by a jumper cable from the CPU card to the front panel. A DMA protocol is specified which provides overlap of the control lines at the beginning and end of the transition between permanent and temporary masters. This allows the address, data, and control buses to settle before information is transferred.

As a bit of personal testimony, I implemented the new DMA protocol on my own system, which includes a Digital Systems dual floppy disk interfaced to a M ITS Altair 8800, using DMA for disk transfers. The soft error rate, presumably due to glitching on the positive true logic lines, dropped from a situation where a file would be seriously munged in a few hours to the present situation where I can work for days on end without an observable error.

We have observed a new typographic convention in publishing the proposed standard. The use of an overbar to denote electrically low active or negative true logic lines has been replaced by a postfix asterisk to avoid confusion with Boolean negation and perm...