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Barriers to Wafer-Scale Integration Disclosure Number: IPCOM000131423D
Original Publication Date: 1979-Jul-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 3 page(s) / 20K

Publishing Venue

Software Patent Institute

Related People

Norman Delano: AUTHOR [+3]


The barriers inhibiting the commercial application of WSI are no longer technical ones---they are instead certain attitudes long embedded in the technical community.

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Barriers to Wafer-Scale Integration

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Norman Delano

The barriers inhibiting the commercial application of WSI are no longer technical ones---they are instead certain attitudes long embedded in the technical community.

The original version of WSI was the concept of discretionary wiring) pioneered by Texas Instruments over ten years ago.' Another variation on this theme was the pad relocation techniques of Hughes. While other firms have investigated probing and zapping approaches to WSI, these techniques are essentially static -- the wafer is partially connected before it is probed and then an interconnect technique is applied to connect only the good circuits. These latter steps typically require extra processing, leading to the attitude that WSI is more expensive than conventional IC test/ dice /package / retest techniques . This view relegates WSI to military equipment where the price premium is offset by the density advantages.

Lately, a dynamic WSI has been proposed3 4 in which the interconnect step is done with active logic, eliminating the probe and static approach. But a number of barriers -- in attitude -- must be overcome before the technical community will fully accept dynamic WSI.



Technical people see low yield as a barrier to WSI. WSI yield is a function of three basic components - - device, module. and bus. The semiconductor industry has device yield well in hand. Since most defects are a random function of area, module yield can be controlled by restricting the size of the module. Various yield curves discussed in the literature suggest that for a large percentage of good modules on a wafer, a small module (say, 100 x 100 mils) should be used.

The final contributor to yield is the interconnect and power bus, which affects wafer yield rather than module yield. Although not generally recognized, bus yield is quite controllable by trading bus size for transfer time s In the limit, a twowire bus for a memory wafer is possible by modulating the power line with a selfclocking control/address/data serial transmission. A more practi...