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Off-Line, Buill~in Test Techniques for VLSI Circuits

IP.com Disclosure Number: IPCOM000131504D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 12 page(s) / 70K

Publishing Venue

Software Patent Institute

Related People

Martin G. Buehler: AUTHOR [+4]

Abstract

Jet Propulsion Laboratory, California Institute of Technology

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1982 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Off-Line, Buill~in Test Techniques for VLSI Circuits

Martin G. Buehler and Michael W. Sievers

Jet Propulsion Laboratory, California Institute of Technology

Using redundant on-chip circuitry improves the testability of an entire VLSI circuit. This study compares five techniques applied to a two-bit ripple carry adder.

Testing integrated circuits involves either a test for structural integrity or a test for proper circuit performance. A structural integrity test verifies that a circuit is fault free by using selected tests to detect the presence of faults, which are defined to be any disruptive changes in a circuit. A fault may cause zero, one, or more errors depending on its location, the state of the circuit, etc. An error is a corruption of any single line logic value. Performance testing establishes that the circuit performs its intended function at the specified speed, power dissipation, etc.

This article evaluates five built-in test techniques that can be used to verify the structural integrity of VLSI circuits. Both classical stuck-at faults and non-classical faults, such as bridging faults (shorts), stuck-on-x faults where x may be 0, 1, or vary between the two, and parasitic flip- flop faults, occur in IC structures. ~ We will assume a stuck-at fault model, however, to simplify the analysis of the testing techniques. The techniques considered -- self- oscillation, self- comparison, partition, scan path, and built-in logic block observer (BILBO) -- represent five basic approaches to off-line testing.

Two basic approaches: external and built~in

The techniques discussed here are applicable to digital circuits. A review of testing techniques can be found in the work of Akers2 and Muehldorf and Savkar.3 A taxonomy of digital test techniques is shown in Figure I where the unit- under-test may be tested using either a built-in or external approach.4

(Image Omitted: Figure 1. Digital test technique taxonomy derived from Clary and Sacane.4)

(Image Omitted: Figure 2. Finite state machine.)

(Image Omitted: Figure 3. Block diagram representation of the adder cir. cult shown in Figure 4. The bits to be added are alas and b1bo; the sum is s1s0, and the carry bits are c2 and C1.)

External approach.

When tested by the external test approach, the unit-under-test can be removed from the host system and tested with automatic test equipment. Alternatively, the system can be reconfigured (by removing or adding various connections) to aid in the testing process.

IEEE Computer Society, Jun 01, 1982 Page 1 IEEE Computer Volume 1...