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Workshop Report: VLSI Development Techniques

IP.com Disclosure Number: IPCOM000131505D
Original Publication Date: 1982-Jun-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 4 page(s) / 21K

Publishing Venue

Software Patent Institute

Related People

True Seaborn: AUTHOR [+3]

Abstract

IBM Improving the performance and density of dynamic RAMchips during the 1980's will require the use of aggressive submicron lithography, very thin oxides, and improved isolation. Testability is what you promise the customer that you will build into a system, but it is the first thing to go when the going gets tough."; How to deal with this early test maxim was just one of the subjects addressed at the Twelfth Annual Computer Elements Committee Workshop, held in Mesa, Arizona, November 30- December 3.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1982 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Workshop Report: VLSI Development Techniques

IBM
Improving the performance and density of dynamic RAMchips during the 1980's will require the use of aggressive submicron lithography, very thin oxides, and improved isolation.

Testability is what you promise the customer that you will build into a system, but it is the first thing to go when the going gets tough."

How to deal with this early test maxim was just one of the subjects addressed at the Twelfth Annual Computer Elements Committee Workshop, held in Mesa, Arizona, November 30- December 3.

Meeting to discuss emerging device technologies for the 80's, some 82 representatives from 30 companies and universities participated in the workshop, which opened with a keynote session on "The Architectural and Design Considerations for a Satellite System Employing Time Division Multiple-Access Techniques." Speakers at this session stressed the system, technology, and schedule tradeoffs that have to be considered in designing such a system -- one that uses a relatively expensive fixed- bandwidth transmission channel. These tradeoffs can affect such things as voice quality, buffer storage, and frame synchronization design parameters.

Session 1: Technology implementation for supercomputers and networking

Performance evaluation of network elements using CMOS shows them to be compatible with high-speed array processors for military applications. As a result, signal processing architectures may take a more distributed form in the future. (Examples of military, imaging, and medical applications were discussed at the conference.)

Medical signal-processing needs, which tend to equal or exceed those of present-day military requirements in speed and computational complexity, are likely to parallel those in the military arena. This parallel will most readily be seen in the design of special-purpose, high-speed computers -- used in devices such as CAT scanners -- that are comparable to image processing mainframe elements.

Session 2: High performance packaging and communications

This session included discussions of 10-to 14-MIPgeneral- purposecomputers and a high- performance military signal processor. The 14-MIP machine achieved 350-ps propagation delays and chip densities of 1300 gates using forced-air cooling across finned heat studs. In the military machine, packaged chip heat stacks are held in copper collets within an aircooled channel. Both of these cooling approaches achieve thermal impedances of about 6 C per watt (junction to air).

IEEE Computer Society, Jun 01, 1982 Page 1 ...