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The Cm * Testbed

IP.com Disclosure Number: IPCOM000131538D
Original Publication Date: 1982-Oct-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 20 page(s) / 68K

Publishing Venue

Software Patent Institute

Related People

Edward F. Gehringer: AUTHOR [+5]

Abstract

Although multiprocessors are theoretically cost-effective and reliable, we aren't really using them. Experiments with a SO-processor architecture are uncovering practical ways to realize these benefits. Interest in multiprocessor architecture has growr steadily over the past ten to fifteen years. With VLS technology we can build multiprocessors that are sub stantially larger than present computers to solve prob Iems that cannot be solved today. Yet despite the substan tial number of multiprocessor designs, only a few multi processors have been built with a high degree ol parallelism, say thirty or more processors. Although multiprocessors appear to have cost/performance and reliability benefits, the computing community has relatively little experience in their actual use. Consequently, little is known about how well the potential of multiprocessors can be realized, which is exactly the thrust of the Cm. research project.

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This record contains textual material that is copyright ©; 1982 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

The Cm * Testbed

Edward F. Gehringer, Anita K. Jones, and Zary Z. Segall

Carnegie-Mellon University

Although multiprocessors are theoretically cost-effective and reliable, we aren't really using them. Experiments with a SO-processor architecture are uncovering practical ways to realize these benefits.

Interest in multiprocessor architecture has growr steadily over the past ten to fifteen years. With VLS technology we can build multiprocessors that are sub stantially larger than present computers to solve prob Iems that cannot be solved today. Yet despite the substan tial number of multiprocessor designs, only a few multi processors have been built with a high degree ol parallelism, say thirty or more processors.

Although multiprocessors appear to have cost/performance and reliability benefits, the computing community has relatively little experience in their actual use. Consequently, little is known about how well the potential of multiprocessors can be realized, which is exactly the thrust of the Cm. research project.

We can view a distributed system as being composed of an architectural component and a behavioral component. The first component consists of hardware, firmware, and software elements, and the relationships between them. The behavioral component is characterized by the way the architecture acts in the presence of a workload. The architectural component should be flexible, and the behavioral component should provide a controllable and measurable behavior.

These two characteristics are embodied in the Cm* testbed, which has a programmable interconnection network for hardware-architecture flexibility. The two operating systems StarOS and Medusa provide/adaptable mechanisms and policies for running experiments with application programs. The workload, the measurement tools, and the experimentation control are integrated into an experimentation environment, which complements the other support programs such as compilers and loaders with facilities for specifying, monitoring, and analyzing experiments.

The Cm# project has successfully constructed a 50- processor multiprocessor and two operating systems, thus

demonstrating the feasibility of several aspects of multiprocessing. In this article we describe not only Cm* hardware and software but also experimental results, how well various algorithm structures exploit the potential parallelism of the Cm*, and the results of extended measurements on the hardware itself.

The Cm* experimentation environment

Cm* hardware.

IEEE Computer Society, Oct 01, 1982 Page 1 ...