Browse Prior Art Database

Image Processing on the Massively Parallel Processor

IP.com Disclosure Number: IPCOM000131579D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 7 page(s) / 29K

Publishing Venue

Software Patent Institute

Related People

J. L. Potter: AUTHOR [+3]

Abstract

The speed and power of the MPP promise the development of new image processing techniques -- real-time, time-varying scene analysis, for example, where the sensor interacts with the scene.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 15% of the total text.

Page 1 of 7

THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1983 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Image Processing on the Massively Parallel Processor

J. L. Potter,

Kent State University

The speed and power of the MPP promise the development of new image processing techniques -- real-time, time-varying scene analysis, for example, where the sensor interacts with the scene.

The MPP, a single instruction, multiple data parallel computer with 16K processors being built for NASA by Goodyear Aerospace, can perform over six billion eightbit adds and 1.8 billion eight-bit multiplies per second. Its SIMD architecture and immense computing power promise to make the MPP an extremely useful and exciting new tool for all types of pattern recognition and image processing applications. The SIMD parallelism can be used to directly calculate 16K statistical pattern recognition results simultaneously. Moreover, the 16K processors can be configured into a two-dimensional array to efficiently extract features from a 128x 128 subimage in parallel. The parallel search capability of SIMD architectures can be used to search recognition and production rules in parallel, thus eliminating the need to sort them. This feature is particularly important if the rules are dynamically changing. Finally, the MPP's computing power and extreme flexibility will allow the development of new techniques for scene analysis -- realtime scene analysis, for example, in which the sensor can interact with the scene as needed.

To support its high computation rate, the MPP has an l/O rate of 320M bytes per second. Table I presents additional statistics on the MPP, and a recent photograph of it appears in Figure 1. Delivery of the MPP was scheduled for December 1982.

Figure 2 shows the organization of the MPP's three basic components: the sequential controller, parallel array, and staging memory. The sequential controller is a high-speed sequential computer with its own internal arithmetic and logical capability. Its primary function is to store and sequence through programs. The MPP's basic cycle rate is 100 ns. The sequential controller is connected to the parallel array by a set of interface registers, which are used to send instructions, parameters, and constants to the parallel array and to pass results back to the sequential controller. The sequential controller also provides the control interface to peripherals and other computers.

The parallel array itself consists of 16K (16,384) microprocessors, designed by Goodyear Aerospace using LSI technology, interconnected in a 128 x 128 configuration. Each instruction sent to the parallel array by the seque...