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Computer Packaging Workshop Report: Interconnection Costs Will Be Dominant in the BO's

IP.com Disclosure Number: IPCOM000131581D
Original Publication Date: 1983-Jan-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 4 page(s) / 21K

Publishing Venue

Software Patent Institute

Related People

John W. Balde: AUTHOR [+3]

Abstract

Vice Chairman, Technical Liaison IEEE Computer Society Technical Committee on Computer Packaging

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1983 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

Computer Packaging Workshop Report: Interconnection Costs Will Be Dominant in the BO's

John W. Balde,

Vice Chairman, Technical Liaison IEEE Computer Society Technical Committee on Computer Packaging

The IC industry has so reduced silicon costs and IC development time that a silicon foundry can now provide twoweek delivery. Yet the printed circuit board or the interconnection substrate may take six months to fully implement, and its reliability is not yet adequately addressed. This incomparability and the increasing cost of interconnection were principal concerns at the spring workshop of the IEEE Computer Society's Computer Packaging Committee, held at Split Rock, Pennsylvania, May 26-28, 1982.

The workshop's theme was "Packaging Technology for the Future," and Michael Godfrey, director of research at Sperry Univac, Blue Bell, Pennsylvania, touched on many of the group's concerns in his keynote speech. Packaging considerations are central to the organization of new systems, but selecting practical ideas from all available options requires an understanding of all the possible structures and their economic trade-offs. Furthermore, Godfrey noted, this understanding of the trade-off choices and their optimization must occur before allocation of resources. We cannot ah ford, he said, solutions like the Picturephone that solve the technical problem but are not worth the resource cost.

CDC's hole grid array.

Among the speakers addressing the interconnection problem was Doug Carlson, who discussed Control Data Corporation's latest supercomputer design. The complete computer has over 80 modules -- all did ferent -- of 100 chips each, and each chip has over 1500 gates, 90 I/O connections, and 8 watts maximum power dissipation.

With modules costing from $20,000 to $30,000 each, stocking spares at the module level no longer makes sense. So CDC decided, as have many other firms, to provide field- replaceable spares at the gate array or chip carrier level. Stocking 20 to 30 gate arrays does achieve acceptable, low inventory costs, but maintenance by changing gate-array chip-carrier packages also requires that they be readily unpluggable.

Control Data's solution is to use a new package, made for them by NTK, that can best be described as a hole grid array package -- that is, a pin grid array package with the pins replaced by holes through the ceramic substrate. These packages are pushed down over a "bed of nails" array of compliant pins on the printed circuit board that make contact to the holes of the ceramic carrier. These pi...