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IEEE Design Automation Workshop Report: Where is Computer- Aicied Design Going?

IP.com Disclosure Number: IPCOM000131606D
Original Publication Date: 1983-May-01
Included in the Prior Art Database: 2005-Nov-11
Document File: 6 page(s) / 27K

Publishing Venue

Software Patent Institute

Related People

Donald Oestreicher: AUTHOR [+3]

Abstract

The 1982 IEEE Design Automation Workshop, held October 6-8 at the Kellogg Center at Michigan State University, consisted of the following five sessions: architecture level design systems, logic design automation, testing, engineering workstations, and technology design rules. Architecture level design systems. Among the systems presented was the system compiler project at GTE Labs. The project goal is the development of a system compiler that ";automatically transforms a specification into an equivalent system of hardware and software."; However, GTE recognizes the difficulty of this task and is investigating three approaches with lesser degrees of automation: (1) manual synthesis, where correctness depends on the designer's wits; (2) manual synthesis with verification, where an automatic system checks for mistakes, using either statistics as in testing or exact comparisons with some schema describing the target; and (3) constrained manual synthesis, where the synthesis process is automatically monitored to prevent error introduction. The project is starting at the third level -- constrained manual synthesis. Project personnel have outlined an interactive system compiler that uses a knowledge base, system requirements, and human input to produce software, firmware assemblies, and ICs. Important project concerns include database management for requirements and knowledge databases and selection of the optimal architecture generation procedure.

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THIS DOCUMENT IS AN APPROXIMATE REPRESENTATION OF THE ORIGINAL.

This record contains textual material that is copyright ©; 1983 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Contact the IEEE Computer Society http://www.computer.org/ (714-821-8380) for copies of the complete work that was the source of this textual material and for all use beyond that as a record from the SPI Database.

IEEE Design Automation Workshop Report: Where is Computer- Aicied Design Going?

Donald Oestreicher

Valid Logic Systems

The 1982 IEEE Design Automation Workshop, held October 6-8 at the Kellogg Center at Michigan State University, consisted of the following five sessions: architecture level design systems, logic design automation, testing, engineering workstations, and technology design rules.

Architecture level design systems.

Among the systems presented was the system compiler project at GTE Labs. The project goal is the development of a system compiler that "automatically transforms a specification into an equivalent system of hardware and software." However, GTE recognizes the difficulty of this task and is investigating three approaches with lesser degrees of automation: (1) manual synthesis, where correctness depends on the designer's wits; (2) manual synthesis with verification, where an automatic system checks for mistakes, using either statistics as in testing or exact comparisons with some schema describing the target; and (3) constrained manual synthesis, where the synthesis process is automatically monitored to prevent error introduction.

The project is starting at the third level -- constrained manual synthesis. Project personnel have outlined an interactive system compiler that uses a knowledge base, system requirements, and human input to produce software, firmware assemblies, and ICs. Important project concerns include database management for requirements and knowledge databases and selection of the optimal architecture generation procedure.

Another system for architecture level design is the University of Illinois' silicon compiler project, which incorporates three levels of IC representation: functional, structural, and geometrical.

The functional level is the requirement specification, and the geometrical level is the mask description. In the university's system, the functional level is described with data flow diagrams. The structural level sits between the functional and geometrical levels. Logic synthesis transforms functional to structural, layout tools transform structural to geometrical, and a silicon compiler goes directly from functional to geometrical. The system focuses on functional decomposition -- the chip floor plan. Once a floor plan is chosen, the silicon compiler completes the chip using cell abutment; no routing or placement is required.

Logic design automation.

Design is a non- monotonic process. At each step, previous design details might be invalidated. The three general thr...