Browse Prior Art Database

Oxygen Donors as a Barrier to Copper Diffusion in the Wafer Thinning Process

IP.com Disclosure Number: IPCOM000131681D
Publication Date: 2005-Nov-14
Document File: 4 page(s) / 158K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that uses the oxygen (or thermal) donors in high resistivity CZ silicon (i.e. greater than ~10 ohm) to switch the doping in the bulk of the wafer from P-type to N-type. Benefits include preventing copper contamination.

This text was extracted from a Microsoft Word document.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 54% of the total text.

Oxygen Donors as a Barrier to Copper Diffusion in the Wafer Thinning Process

Disclosed is a method that uses the oxygen (or thermal) donors in high resistivity CZ silicon (i.e. greater than ~10 ohm) to switch the doping in the bulk of the wafer from P-type to N-type. Benefits include preventing copper contamination.

Background

Some stacked die products that undergo a back grind/CMP (die thinning) process in assembly experience copper contamination, which causes reliability issues with gate oxide charge retention. High resistivity silicon wafers used for RF applications experience similar copper contamination at the assembly if the die thinning option is used for the RF products. Third-party investigations indicate that some DRAM vendors are currently experiencing similar problems with thinned and stacked DRAMs. Figure 1a and 1b show copper contamination in the back side die thinning process.

Attempts to prevent the copper contamination during the die thinning process have had limited success. One technique adds a deep N-well which acts as a barrier for the diffusion of copper contamination from the back of the wafer during the die thinning. Since copper diffuses as a positive ion, and since the N-well has a built-in (~700mV) positive bias, it repels copper. However, this is not completely effective since not all the circuits are protected by the N-well.

General Description

Figure 2a, 2b, and 2c refer to steps for making the disclosed method work for P-/P- epitaxial wafers. Figure 3a, 3b, and 3c refer to steps for making the disclosed method work for P- non-epitaxial wafers with a high temperature (~1200C) Ar or H2 anneal. Steps for this invention:

 

  1. The interstitial oxygen present in Czchrolaski grown silicon crystal acts as an N-type dopant if the wafer is annealed at temperatures around 400 to 450°C. For lightly doped P-type silicon, the oxygen donors switch the silicon doping from a P-type to an N-type.
  2. Engi...