Browse Prior Art Database

Method for performing through-silicon interconnects prior to IC fabrication

IP.com Disclosure Number: IPCOM000131682D
Publication Date: 2005-Nov-14
Document File: 5 page(s) / 125K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for preforming through-silicon interconnects prior to integrated circuit (IC) fabrication. Benefits include improved functionality, improved performance, improved yield, and improved process simplification.

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Method for performing through-silicon interconnects prior to IC fabrication

Disclosed is a method for preforming through-silicon interconnects prior to integrated circuit (IC) fabrication. Benefits include improved functionality, improved performance, improved yield, and improved process simplification.

Background

      A requirement exists for a silicon (Si) etch process that consistently and uniformly contacts the shallow trench isolation (STI) layer without damage to the circuit. The conventional solution exposes a completed IC to processing steps that can damage the circuit.

      The conventional solution can be implemented using the following steps:

1.   Fabricate the IC.

2.   Bond the wafer (IC side) to the carrier.

3.   Backgrind the wafer (non-IC side).

4.   Perform a dry Si etch process to the contact bottom of the IC followed by an oxide etch to the contact metal layers.

5.   Fill vias with metal to form through-silicon interconnections.

      The back-side contacts are used for die-stack interconnections without wire bonding. Back-side connections to vias can damage transistors associated with ICs.

General description

              The disclosed method preforms through-silicon vias prior to IC creation. They connect vias to any metal layer in a stack. Backside vias are exposed by back-grinding and dry Si etch.

              The key elements of the disclosed method include:

•             Through-silicon vias created prior to IC fabrication

•             Interconnection of Si vias to different metal layers

•             Backside grinding to expose backside interconnects

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to preforming through-silicon interconnects prior to IC fabrication
•             Improved performance due to creating the interconnections during microprocessor formation

•             Improved performance due to eliminating contact alignment issues that occur from back-side connection

•             Improved performance due to relieving thin Si wafer stress from back-grinding by using dry etching with back-side contacts

•             Improved yield due to decreasing damage to finished microprocessors by requiring only backgrinding and Si dry etch to expose vias

•             Improved yield due to eliminating transistor damage from contacting the vias from the backside

•             Improved process simplification due to reducing the number of performed after IC formation

Detailed description

              The disclosed method preforms through-silicon vias prior to IC creation. The process uses standard fabrication methods, including the following:

•             S...