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Wrapper cell for asyncronous domain crossings in at-speed structured test

IP.com Disclosure Number: IPCOM000131729D
Original Publication Date: 2005-Nov-17
Included in the Prior Art Database: 2005-Nov-17
Document File: 2 page(s) / 134K

Publishing Venue

IBM

Abstract

Disclosed is a new wrapper design for asynchronous crossings in circuits having multiple asynchronous domains. The new wrapper aids in testing multiple asynchronous domains simulataneously when using functional clocks for test.

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Wrapper cell for asyncronous domain crossings in at -speed structured test

At-speed structured test (ASST) uses on-chip PLLs to launch and capture test data using functional clocking. Different clock domains may receive functional clocks from different asynchronous PLLs. In test generation, expected data in capture latches of one clock domain that receive data from launch latches in another clock domain may be predicted that may not be observed in hardware, resulting in fails at the tester.

The proposed method prevents data from one clock domain reaching the latches of another clock domain in ASST. Thus incorrect expected data for multicycle asynchronous paths is not predicted.

The known solutions to the problem of testing asynchronous clock domains are a) to test only one domain at a time by holding other domains dormant, and b) to stagger clocks to different clock domains. The drawback to these known solutions are as follows. Firstly, by testing only one domain at a time or by staggering clocks, testing time and test pattern counts can increase significantly. This increases test cost. Secondly, for a circuit-under-test that requires a continuous free-running clock, it may not be posible to stagger the clock pulses to this circuit while another clock domain is being tested. Finally, the complexity of test generation for serially-staggered clocks to different domains rises significantly.

This disclosure presents a new wrapper cell design for asynchronous domains...