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Method for double-sided silicon processing for SCSPs

IP.com Disclosure Number: IPCOM000131783D
Publication Date: 2005-Nov-18
Document File: 8 page(s) / 173K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for double-sided silicon processing for a stacked chip scale packages (SCSPs). Benefits include improved functionality, improved performance, and improved reliability.

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Method for double-sided silicon processing for SCSPs

Disclosed is a method for double-sided silicon processing for a stacked chip scale packages (SCSPs). Benefits include improved functionality, improved performance, and improved reliability.

Background

      Market trends require flash products with large capacities but small and thin form factors. Stacked dice increase the capacity, but also increase the package height, assembly cost, and assembly risk. Additionally, the assembly process impacts the circuit performance by increasing the Gm shift and the read window budget (RWB), especially for multilevel cell (MTL) devices.

      Conventional flash die designs have integrated circuits (ICs) on the frontside of the wafer (see Figure 1).

              To increase capacity conventionally, multiple dice are stacked (die on die) or packaged externally. However, cost-effective methods, the elimination of Gm shift "Transconductance of the devices", and improved read window budgets are required.

General description

              The disclosed method fabricates double-capacity flash devices and transistor device layers on both sides of the wafer. To create double-capacity flash devices, two copies of the ICs are created on the front and back sides of the wafer. The circuits are connected by through-silicon vias (TSVs). As a result, 2+1 flash product (2 dice+1 spacer) capacity is achieved on one die. Because assembly cost and risk are greatly reduced, the thickness can be increased, which improves the Gm shift and read window budget.

      To create transistor device layers on both sides of the wafer, the disclosed method creates half of the ICs on one side of the wafer and half on the other side of the wafer. Memory is placed on-board without routing through the package. The silicon (Si) process is optimized for each side.

              The key elements of the disclosed method include:

•             Flash circuit fabrication on both wafer sides

•             Connection by through-silicon vias

•             Wafer-thinning technology

•             Placement of memory on the back of a control die

•             Connection by etching through the back side of the die and through the transistor area to the device layer

•             Fabrication of the device layers on both sides of the silicon

•             Formation and filling of vias inside the silicon

•             Deposition of metal layers on the silicon back side (using conventional methods)

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to doubling the flash capacity

•             Improved functionality due to reducing the package height because one die supplies the capacity of two conventional dice

•             Improved functionality due to enabling die stacking for packaging

•             Improved functionality due to reducing the usage of wafer surface area by placing half of the ICs on one side of the wafer and half on the other si...