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Clock Recovery Algorithm Using a PCM Data Stream to Detect the Presence or Absence of an External System Clock

IP.com Disclosure Number: IPCOM000131787D
Publication Date: 2005-Nov-18
Document File: 2 page(s) / 28K

Publishing Venue

The IP.com Prior Art Database

Abstract

This invention applies generally to the field of digital electronics and specifically to the field of data communications. We have a DSP/codec connected to a Bluetooth radio chip. The DSP can generate its own clock internally, but this is too slow and the clock needs to be synchronized to the Bluetooth radio’s clock. Accordingly, the DSP/codec uses the Bluetooth radio’s clock, which is much faster, as the system clock to improve the MIPS available for DSP and to ensure that the audio data communicated between the DSP and the radio is always synchronized. However, if the radio does not have an active link open to another Bluetooth radio device, such as a cell phone handset, then the radio goes into a condition known as “deep sleep” which disables the main high-speed clock. When the radio’s clock is disabled, the DSP stops and cannot be revived until the clock restarts. This would be fine except that when the clock does restart, the clock waveform grows gradually, rather than provide a clean start. This gradual clock start behavior can be misread by the DSP and cause some parts of the DSP to malfunction. One solution is to not permit the radio to enter the deep sleep mode, which means the clock will never stop. This has a significant negative impact on talk time. Another solution is to always reset the DSP when the clock restarts. The time to finish the power-up reset initialization procedure is normally too long for most applications. A third solution is to use an external master oscillator to operate both the radio and the DSP. This requires more power also and more circuit board space. This invention takes advantage of the fact that the audio data from the radio stops a few milliseconds before the clock stops. The DSP senses the audio data has stopped and immediately switches from the external fast clock to its internal slow clock. Transitions between the two clocks are guaranteed to be clean by the DSP vendor. A preferred method of sensing the loss of audio data is via a periodic interrupt that reads whether any audio data was transferred in the period since the last interrupt. Other means can be used by anyone skilled in the art. Once the DSP is running from its internal clock, it cleans all of the residual audio data out of its internal buffers, resets the buffer pointer counters and then waits for the audio data clock to resume. When the DSP senses the resumption of the audio data stream, preferentially but not necessarily done by means of an interrupt, the DSP can assume that the radio has woken up from the deep sleep mode and the high-speed clock is now available again. Accordingly, it switches back to the external clock and resumes processing the audio data.

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Title

Clock Recovery Algorithm Using a PCM Data Stream to Detect the Presence or Absence of an External System Clock

Abstract

This invention applies generally to the field of digital electronics and specifically to the field of data communications.

We have a DSP/codec connected to a Bluetooth radio chip. The DSP can generate its own clock internally, but this is too slow and the clock needs to be synchronized to the Bluetooth radio’s clock. Accordingly, the DSP/codec uses the Bluetooth radio’s clock, which is much faster, as the system clock to improve the MIPS available for DSP and to ensure that the audio data communicated between the DSP and the radio is always synchronized.

However, if the radio does not have an active link open to another Bluetooth radio device, such as a cell phone handset, then the radio goes into a condition known as “deep sleep” which disables the main high-speed clock. When the radio’s clock is disabled, the DSP stops and cannot be revived until the clock restarts. This would be fine except that when the clock does restart, the clock waveform grows gradually, rather than provide a clean start. This gradual clock start behavior can be misread by the DSP and cause some parts of the DSP to malfunction.

One solution is to not permit the radio to enter the deep sleep mode, which means the clock will never stop. This has a significant negative impact on talk time.

Another solution is to always reset the DSP when the clock restarts. The time to finish the power-up reset initialization procedure is normally too long for most applications....