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Power density aware power bus pruning in VLSI chips

IP.com Disclosure Number: IPCOM000131824D
Original Publication Date: 2005-Nov-21
Included in the Prior Art Database: 2005-Nov-21
Document File: 2 page(s) / 8K

Publishing Venue

IBM

Abstract

Power density aware pruning of power distribution structures in VLSI chips

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Power density aware power bus pruning in VLSI chips Power density aware power bus pruning in VLSI chipsPower density aware power bus pruning in VLSI chips Power density aware power bus pruning in VLSI chips

Disclosed is a methodology to prune power distribution structures in VLSI chips, while observing a power density budget. This methodology can be applied to power busses, power grids, or any other regular distribution structure.

    The density requirement for power distribution structures in VLSI chips is highly dependent on the type, number and activity of circuits located in a given area on the die. Furthermore, it is a function of the routing capacitance, which has to be driven by these circuits, and their switching factors.

    The starting point for the disclosed methodology is a die with a robust and fully populated power bus structure. An exemplary structure might be designed to allow a 90% placement density with a typical switching factor of 0.1. This would result in a structure that is consuming a certain percentage of routing resources on each level of metalization:

33 % routing resources on metal 1 17 % routing resources on metal 2 13% routing resources on metal 3 17 % routing resources on metal 4 17 % routing resources on metal 5 28 % routing resources on metal 6 28 % routing resources on metal 7

    Circuits are now placed with conventional placement tools. Ideally, the placement step is congestion driven to reduce placement density in areas with high routing density.

    After circuits are placed, actual power density is estimated in order to calculate the required local power density.

    The local power density analysis can be performed in different ways, each with a different trade-off between accuracy and speed.
A) High accuracy / low speed:

  Dividing the chip area into bins and running a detailed, transient, power density analysis for each bin.
B) Medium accuracy and speed:

Dividing the chip area into bins and assigning a switching vs. quiet capacitance ratio for each of the bins.
C) Low accuracy / high speed:

Assuming a correlation between placement density and power density.

    Whichever method is chos...