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802.16 FCH Coding – Decoding Tail-Biting Convolutional Codes

IP.com Disclosure Number: IPCOM000132033D
Original Publication Date: 2005-Nov-29
Included in the Prior Art Database: 2005-Nov-29
Document File: 5 page(s) / 276K

Publishing Venue

Motorola

Related People

T. Keith Blankenship: AUTHOR [+2]

Abstract

The encoding process for the downlink frame prefix in the IEEE 802.16 standard first re-peats the prefix, randomizes the repeated prefix, and then encodes the resulting sequence with a rate-1/2 tail-biting convolutional code. By exploiting the properties of the convolutional code, an improved decoding procedure for the downlink frame prefix can be implemented.

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802.16 FCH Coding – Decoding Tail-Biting Convolutional Codes

T. Keith Blankenship and Vip Desai

Abstract

The encoding process for the downlink frame prefix in the IEEE 802.16 standard first repeats the prefix, randomizes the repeated prefix, and then encodes the resulting sequence with a rate-1/2 tail-biting convolutional code. By exploiting the properties of the convolutional code, an improved decoding procedure for the downlink frame prefix can be implemented.

Background

The downlink frame prefix (DL_Frame_Prefix) is a 24-bit message containing information about the downlink map (DL-MAP) that each subscriber station must process [1]. The downlink frame prefix is mapped into the frame control header (FCH) as shown in Figure 1. The randomizer 120 adds (bitwise exclusive-ORs) a pseudo-noise sequence to the repeated DL_Frame_Prefix message (output of the block repeater 110) before the rate-1/2 tail-biting convolutional encoder 130. The encoded sequence is bit interleaved in 140 before modulation by the QPSK modulator 150. The modulated symbols are block repeated in 160 before transmission.

The FCH receiver processing in Figure 2 inverts the transmitter processing. To invert the post-encoder 4× block repetition, the repeated symbols are typically max-ratio combined 210, thereby improving the signal-to-noise ratio into the convolutional decoder 230. The de-repeated symbols are typically converted into log-likelihood ratios (LLRs) in 220 for the decoder 230. The decoder 230 decodes the 96 LLRs to produce a 48-bit block. Subsequently, that 48-bit block is de-randomized by 240. Since the DL_Frame_Prefix message is repeated before encoding, the de-repeat block 250 can declare an error when the first and second halves of the de-randomized 48-bit block are not identical.

Improving Decoder Performance

While the described decoding method provides for error detection, it is possible to improve the error correction performance by exploiting the properties of the convolutional encoder. Denoting the addition process by “+” and the encoding process by “·”, the encoder output sequences H1 and H2 can be described as

                                                                                                               (1)

for i = 1,2, where D is the repeated DL_Frame_Prefix message, R is the randomization sequence, and Gi is the i-th encoder polynomial. Hence, the encoding of the randomization sequence can be viewed as independent of the encoding of the repeated message.

The tail-biting convolutional encoder is initialized using the last m bits of the input sequence, where 2m is the number of encoder states. Exploiting encoder linearity in (1), the tail-biting constraint produces a repeated output for the repeated message. To illustrate, denote the message as di, i = 0,…,23. Hence the input to the 26-state encoder is the sequence d0,…,d18,d19,d20,d21,d22,d23,d0,…...