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Method for a Cu interconnects system with low line resistivity and enhanced EM resistance

IP.com Disclosure Number: IPCOM000132112D
Publication Date: 2005-Dec-01
Document File: 6 page(s) / 136K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a Cu interconnect system with low line resistivity and enhanced electromigration (EM) resistance. Benefits include improved functionality, improved performance, improved yield, and improved cost effectiveness.

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Method for a Cu interconnects system with low line resistivity and enhanced EM resistance

Disclosed is a method for a Cu interconnect system with low line resistivity and enhanced electromigration (EM) resistance. Benefits include improved functionality, improved performance, improved yield, and improved cost effectiveness.

Background

      Conventional Cu interconnection can result in several issues, including the following:

•             Line resistivity increase in narrow features (<100 nm) due to Cu grain boundaries scattering (see Figure 1)

•             EM issues due to the presence of fast diffusion paths on the interfaces, such as liner/Cu and dielectric etch stop (ES), and voids in damascene features due to plating gap-fill issues and physical vapor deposition (PVD) seed overhang

•             Gap fill issues in damascene structures causing voids in Cu lines/vias

      Gap fill issues in damascene process are addressed by directly plating copper on barriers, but the technology is not fully developed.

              No conventional solution exists to decrease the Cu line resistivity that results from grain growth constrained s by trench boundaries.

      No conventional solution exists for line/interface issues. The top surface of Cu lines can be passivated by selective metal cap deposition.

      The conventional dual-damascene process includes the following steps:

1.   Deposit an interlayer dielectric (ILD) layer.

2.   Perform lithography to pattern vias.

3.   Etch the vias.

4.   Clean the vias.

5.   Perform lithography to pattern trenches.

6.   Etch the trenches.

7.   Clean the trench sides and bottom.

8.   Deposit a barrier/seed PVD layer.

9.   Perform electroplating (EP) to fill gaps in the Cu layer.

10.         Perform chemical/mechanical planarization (CMP) on the Cu layer.

11.         Create a Co cap layer.

General description

      The disclosed method is a Cu interconnection system with large grain Cu lines that have low resistivity and enhanced EM resistance. The line width is 10x or more wider than conventional lines.

      The key elements of the disclosed method include:

•     Copper lines with large grains

•     Copper lines cladded with an electroless metal cap, such as a Co(Ni)X (where X is W, Mo, B, P and their alloys)

•     Metal plugs of selective electroless metal, such as Ni, Co, Cu and their alloys, in vias

Advantages

      The disclosed method provides advantages, including:
•             Improved functionality due to providing the complete gapfill of unlanded vias by selectively filling metal vias

•     Improved functionality due to fabricating lines using a subtractive process

•     Improved functionality due to reducing Cu line resistivity by 30% or more

•     Improved functionality due to reducing EM by passivating Cu line surfaces with wetted metals, such as Co and Ni

•     Improved performance due to increasing the metal grain size

•...