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Method for off-axis reticle stage functionality for optimizing device performance

IP.com Disclosure Number: IPCOM000132120D
Publication Date: 2005-Dec-01
Document File: 4 page(s) / 62K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for off-axis reticle stage functionality for optimizing device performance. Benefits include improved functionality, improved performance, improved process flexibility, and improved cost effectiveness.

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Method for off-axis reticle stage functionality for optimizing device performance

Disclosed is a method for off-axis reticle stage functionality for optimizing device performance. Benefits include improved functionality, improved performance, improved process flexibility, and improved cost effectiveness.

Background

      Critical lithography steps, such as the transistor gate layer for a microprocessor, play a significant role in the final performance and yield of devices in the integrated circuit (IC) manufacturing process. Devices tend to be very sensitive to small changes in the physical dimensions of the structures that comprise the circuit, especially speed paths, at critical layers. The exposure power distribution across the mask is a process parameter that can significantly influence the cross-device physical dimensions and the performance/yield of devices.

      Power distribution (illumination) of the exposure tool can be moderated a limited number of ways without impacting all processes and/or devices running on the tool. Conventional methods to manipulate the illumination across the mask are typically radially symmetric. They are not always independently tunable to each device mask, which prevents full optimization on critical layers’ tools.

              Conventionally, optic movement within the tool shapes the exposure illumination incident on the mask. Adjustments tend to be symmetric around the center of the lens/mask. The lens and reticle centers effectively overlap during exposure. However, they do not enable nonsymmetrical illumination across the mask. These optic adjustments can be process-layer specific but tend not to be device specific, which may be a requirement (see Figure 1).

      A conventional solution to exposure limitation is the insertion of correction optics in the illumination path to reshape the power distribution profile. The optics change impacts all processes and devices running on the tool. Correction optics are radially symmetric around the lens center but are not process or device specific.

      FMAX is the frequency speed of an individual die on a wafer. ACLEN is the channel length of transistors on a die. The value of FMAX is dependent on the ACLEN value as a negative linear relationship.

      Conventional processing indicates the illumination profile at the transistor gate lithography physical layer (PLY) is a significant modulator of the FMAX in relation to the ACLEN. A manufacturing tool that processes the PLY layer provides a higher FMAX performance at a given ACLEN when the illumination profile is not symmetrical, concave upward, and slightly tilted. Transistor gate critical dimensions are modulated by the illumination profile with the result that transistors in the speed paths are slightly smaller than those not in speed-path areas. Dice from these tools perform at a higher speed relative to other PLY tools for the same overall leakage across the die. Additionally, duri...