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Fabricating Self-Aligned Stacked CMOS Field-Effect Transistors and Logic Devices

IP.com Disclosure Number: IPCOM000132325D
Publication Date: 2005-Dec-07
Document File: 3 page(s) / 193K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a totally self-aligned, gate-last process compatible with novel gate electrodes and dielectrics (e.g. metal gates and high-k dielectrics). Benefits include improved flexibility to individually optimize channel doping, chemical composition, and strain conditions.

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Fabricating Self-Aligned Stacked CMOS Field-Effect Transistors and Logic Devices

Disclosed is a method for a totally self-aligned, gate-last process compatible with novel gate electrodes and dielectrics (e.g. metal gates and high-k dielectrics). Benefits include improved flexibility to individually optimize channel doping, chemical composition, and strain conditions.

Background

The following are the issues associated with the current state of the art:

§         Low thermal stability of the novel gate electrode and dielectric stack

§         Minimal flexibility when optimizing the PFET and NFET channel composition

§         Non-trivial integration of novel source/drain junction technologies

§         Footprint difficulties and low-packing density of logic gates, with wide PFETs

§         Prolonged connecting distances between the PFETs and NFETs

§         Asymmetric pull-up and pull-down currents in the logic gates

General Description

The following are the process steps for the disclosed method:

1.      The starting substrate is a bulk silicon wafer with p-type channel doping. An optional pad SiO2 is grown on the silicon, followed by Si3N4 (nitride) layer formation through low-pressure chemical vapor deposition (LPCVD). A low-temperature SiO2 (LTO) film is then deposited by LPCVD on top (Figure 3a).

2.      1st lithography step: part of the LTO/nitride stack is selectively etched away to leave room for the FETs channel stack formation (Figure 3b).

3.      The multi-layer epitaxial SixGe1-x/Si/SixGe1-x channel stack is selectively grown from the channel regions opened during step 2 (Figure 3c). The bottom SixGe1-x layer is thread dislocation-free by limiting its thickness to below the critical thickness at the corresponding SixGe1-x fraction. The middle silicon layer, with desired n-type doping concentration, is grown on the bottom SixGe1-x layer free of dislocations, and shares the same lattice spacing as the silicon wafer. The top SixGe1-x layer has any crystallinity as long as it is thick enough to act as a blockage buffer for subsequent dopant implantation and etching.

4.      The LTO layer is selectively removed without damaging the epitaxial SixGe1-x/Si/SixGe1-x channel stack (Figure 3d).

5.      The N-type dopant is blanket implanted through the nitride layer to form the n+-source/drain junctions for the NFET with the p-type silicon substrate as the channel (Figure 3e). The top SixGe1-x layer on the channel stack blocks the implant from penetrating into the middle silicon layer underneath.

6.      2nd lithography step: The nitride contact trench is etche...