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Carbon Nanotube-Based Capacitor Array for Charge Sensing Applications and Process Flows

IP.com Disclosure Number: IPCOM000132344D
Publication Date: 2005-Dec-08
Document File: 5 page(s) / 396K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method that when implemented in a field-effect transistor (FET) geometry, the low parasitic capacitance leads to faster switching (i.e. low gate delay CV/I). When implemented in a capacitor geometry, the low parasitic capacitance acts as a charge sensor. Benefits include enabling high-frequency operations.

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Carbon Nanotube-Based Capacitor Array for Charge Sensing Applications and Process Flows

Disclosed is a method that when implemented in a field-effect transistor (FET) geometry, the low parasitic capacitance leads to faster switching (i.e. low gate delay CV/I). When implemented in a capacitor geometry, the low parasitic capacitance acts as a charge sensor. Benefits include enabling high-frequency operations.

Background

CNTs are one-dimensional materials with nanoscale diameters, leading to very low CNT capacitance. The parasitic capacitance contributions from macroscopic probe pads is typically 100,000x larger than the intrinsic CNT capacitance. Therefore, the high-frequency operation of CNT-based FETs are limited by the large parasitic capacitances (CP) unless device structures are designed to have a low CP. Also, the reliable measurement of intrinsic device capacitance of CNT-based capacitors is not possible without structures that have a low CP.

General Description

The disclosed method uses CNT structures with low parasitic capacitances. Semiconducting single-walled CNTs with 1-2 nm diameters have an energy band gap in the 0.8-0.4 eV range. Both electrons and holes are expected to have good transport properties, which makes semiconducting CNTs attractive candidates as the channel of FETs. The P-channel CNT/FETs exhibit lower intrinsic gate delay CV/I than their silicon counterparts, due to the ~ 20x higher p-channel effective mobility.

The nanoscale CNT diameter leads to very low CNT capacitance. For example, a 1.4 nm diameter CNT deposited on an oxide with Toxe = 2nm has a capacitance per unit length of CCNT/LCNT ~ 0.2 fF/mm. Therefore, conventional CNTs with length LCNT ~ 1 mm have CCNT ~ 0.2 fF. when source/drain pads (typically 50 mm x 50 mm) are deposited on thin oxides with Toxe = 2nm, the parasitic pad capacitance is CP ~ 40 pF, which is 200,000x larger than CCNT. Therefore, the high-frequency operation of CNT/FETs is limited by CP. Also, the reliable measurement of intrinsic device capacitance CCNT of CNT-based capacitors is not possible when CP is 200,000x larger than CCNT.

Two proposed device structures (one with a global back gate and another one with a local back gate) are shown in Figures 2a and 2b. The important features of these structures are:

1.      Long CNTs grown from catalyst islands by chemical vapor deposition (CVD) to enhance CCNT

2.      Thick oxide layers for depositing the source/drain pads for reducing CP

3.      The p+ silicon wafer or intrinsic i-silicon wafers with p+ implants for back gates

The proposed structures can be also be fabricated in an array format. As shown in Figures 2c and 2d, the arrays of the structures illustrated in Figures 2a and 2b will then have common (global) and independent (local) back gates, respectively.

Process flow for fabricating structure A:

1.      Pattern resist and etch a few micron into the p+ silicon wafer to define alignment markers that are needed for the subsequent lithography steps.

2.      Depo...