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Method for an enhanced self-refresh exit command

IP.com Disclosure Number: IPCOM000132451D
Publication Date: 2005-Dec-16
Document File: 5 page(s) / 31K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an enhanced self-refresh exit command. Benefits include improved functionality and improved reliability.

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Method for an enhanced self-refresh exit command

Disclosed is a method for an enhanced self-refresh exit command. Benefits include improved functionality and improved reliability.

Background

              The procedure for exiting a self-refresh process requires a sequence of commands. The clock must be stable prior to the clock enable (CKE) signal going HIGH. When a self-refresh exit (CKEH) is registered, a delay of a period designated as tXSNR must be satisfied before a valid command is issued to enable internal refreshing. The CKE signal must remain high for the entire self-refresh exit period, tXSRD, for successful operation except for self-refresh reentry (see Figure 1).

              Conventionally, the dynamic random access memory (DRAM) controller must start the DRAM clock before it asserts the CKE signal HIGH. When a CKE glitch occurs, memory is in the self-refresh state, the DRAM clocks are off, and the memory controller has not yet started the automatic refresh. Additionally, the DRAM device stops all internal-counter-based refresh cycles. Due to the lack of any refresh cycles, data decays, gets lost in memory, and causes a system hang.

              External peripherals, such as a wireless card, can induce CKE glitches. For example, a peripheral card can cause a PCI reset glitch on powerup after resuming from standby mode with minimal power maintained for a fast memory startup (S3 power state). Because only the CKE signal input/output (I/O) is enabled on the memory interface in the S3 state, a CKE glitch results in a system hang.

      Peripheral component interface (PCI) is a standard protocol for a 3.3V local interconnect bus. The specification was published as “PCI Local Bus Specification version 3.0 (PCI v3.0)” by PCI-SIG(Reg.TM) on April 19, 2004.

              Double data rate synchronous dynamic random access memory is standardized by “DDR2 SDRAM Specification”, JESD79-2B, which was published by Joint Electronic Devices Engineering Council (JEDEC) January 2005.

Description

              The disclosed method adds an enhanced self-refresh exit command (EnSRE), an EMRS command,...