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Method for dynamic alignment of memory interface data receivers

IP.com Disclosure Number: IPCOM000132455D
Publication Date: 2005-Dec-16
Document File: 2 page(s) / 15K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for dynamic alignment of memory interface data receivers. Benefits include improved functionality and improved performance.

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Method for dynamic alignment of memory interface data receivers

Disclosed is a method for dynamic alignment of memory interface data receivers. Benefits include improved functionality and improved performance.

Background

              Double data rate synchronous dynamic random access memory (SDRAM) is standardized by a specification, “DDR2 SDRAM Specification”, JESD79-2B, that was published January 2005 by Joint Electronic Devices Engineering Council (JEDEC). The specification defines the external timing required for signals, such as the DQ and DQS bus signals.

              An internal receive-enable signal, RCVENB, latches read data. For a design to meet the DDR2 timing specification, the RCVENB signal should be aligned to the middle of the preamble of the DQS signal.

              Conventionally, the RCVENB signal is controlled through a software-accessible or memory-based register. The built-in operating system (BIOS) is responsible for programming a recommended value on boot. Determining the RCVENB command value is a manual process performed by engineers using manual probes with all possible memory combinations with varying memory technologies and loading conditions. This process is very time consuming, labor intensive, and prone to future problems as new memory devices become available. The problem is expected to become increasingly difficult as increased memory slots and channels increase the problem complexity.

Description

              The disclosed method is a hardware design and system BIOS software algorit...