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Method for PCI Express lane breaker test apparatus

IP.com Disclosure Number: IPCOM000132456D
Publication Date: 2005-Dec-16
Document File: 2 page(s) / 39K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for PCI Express lane breaker test apparatus. Benefits include improved functionality, improved performance, and improved reliability.

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Method for PCI Express lane breaker test apparatus

Disclosed is a method for PCI Express lane breaker test apparatus. Benefits include improved functionality, improved performance, and improved reliability.

Background

              PCI Express implementations are standardized by “PCI Express Base Specification 1.0”, which was published by PCI-SIG on July 16, 2003.

              Conventionally, validation of PCI Express lane break/degradation testing is very limited due to the mostly manual methods and the many possible scenarios that are required. A programmable automated solution is required.

Description

              The disclosed method includes an interposer-style test card. It can force the following modes on any positive (P) or negative (N) pair of any transmit (TX) or receive (RX) PCI Express differential lane:

•             Tie high (level or programmable duration)

•             Tie low (level or programmable duration)

•             Open

•             Short P to N

              These modes are programmable and under software control and can be independently controlled for each lane. Each mode can be driven to a specific level or can have a programmable duration. The mode can be set for each lane statically using external DIP switches (see Figure 1).

              The fully deployed solution involves the creation of several physical board skews, including the following:

•             x1 male blade with a x16 add-in card slot (with mechanical support for standard PCIe card form factor...