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Method for a dual-mode output driver circuit with reduced parasitic capacitance

IP.com Disclosure Number: IPCOM000132457D
Publication Date: 2005-Dec-16
Document File: 6 page(s) / 122K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a dual-mode output driver circuit with reduced parasitic capacitance. Benefits include improved functionality and improved performance.

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Method for a dual-mode output driver circuit with reduced parasitic capacitance

Disclosed is a method for a dual-mode output driver circuit with reduced parasitic capacitance. Benefits include improved functionality and improved performance.

Background

              The maximum operating data rate for a dual-mode output driver is lowered by high parasitic capacitance. A low-speed output mode is required for many interfaces to enable low-speed testing, a low-speed bypass mode, or a dual-mode interface compatible with two separate output interface types.

              When an input/output (I/O) interface is required to create output in two modes (dual-mode output), a low-speed output driver is added to the output pad of the high-speed output driver. At any one time, only one of the output drivers is enabled. The disabled output driver adds significant parasitic capacitance to the other driver’s operation, lowering the maximum operating data rate of the high-speed output driver.

      On-die-termination (ODT) is required for the normal high-speed mode of operation. The low-speed mode can be achieved with a minimal increase in the parasitic capacitance. Typical dual-mode transmitters have both high-speed and low-speed drivers connected at the pad with only one or the other enabled at any given time. The addition of the low-speed circuit adds significant parasitic capacitance to the high-speed driver (see Figures 1 and 2).

      Conventionally, the main output mode is the high-speed small-swing differential mode. The lower speed output mode has a higher swing single-ended topology. This configuration enables a single high-speed differential low-swing pair to be reconfigured into two lower speed, larger swing, single ended output drivers. A single-ended large swing driver is added to the standard differential output at each side of the differential pair. In high-speed differential mode, the two single-ended drivers are disabled. In low-speed single-ended mode, the differential high-speed drivers and terminations are disabled. However, the addition of the low-speed single ended drivers to the differential outputs adds significant parasitic capacitance. It lowers the output driver bandwidth and decreases the output signal quality (see Figure 3).

General description

              The disclosed method is a dual-mode output driver circuit with configurable ODT. Its operation minimally impacts the maximum achievable data rate for the high-speed interface.

              The key elements of the disclosed method include:

•             Dual-mode ou...