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Non-Symmetrical CMOS Comparator and Sampler Circuits

IP.com Disclosure Number: IPCOM000132460D
Publication Date: 2005-Dec-17
Document File: 5 page(s) / 435K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for a non-symmetrical comparator/sampler circuit structure that introduces a PVT insensitive and well-controlled comparison threshold voltage in the comparator and sampler circuits. Benefits include a solution that uses a smaller area, consumes less power, and is suitable for very high frequency operations.

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Non-Symmetrical CMOS Comparator and Sampler Circuits

Disclosed is a method for a non-symmetrical comparator/sampler circuit structure that introduces

a PVT insensitive and well-controlled comparison threshold voltage in the comparator and sampler circuits. Benefits include a solution that uses a smaller area, consumes less power, and is suitable for very high frequency operations.

Background

Comparators and samplers are key circuit building blocks, which are widely used in various VLSI circuits and systems. In these applications, single-end or differential signals of high frequency (e.g. 5Gb/s in PCI-E) (please remove) are usually compared with specified threshold levels (e.g. PCI-E Rx samplers, etc.) and sampled. The outputs are then used in the circuit system for various signal processing operations. Figures 1a and 1b show the conventional circuit implementations of the comparators and samplers for differential signals with a zero comparison threshold. Where a matched-input MOS pair is used for signal comparison and sampling, these circuits are commonly used in the high-speed I/O system for signal capture and single-end level peak detection.

In some applications, differential comparators and samplers with non-zero comparison threshold voltages are required. One of the conventional circuit implementations for the non-zero threshold comparison/sampling is shown in Figures 2a and 2b.

Although used in many VLSI systems, the non-zero threshold differential comparator and sampler are highly complex (e.g. two matched input MOS pairs are required). Also, they require dedicated circuits for accurate threshold reference voltage generation. As a result, these circuits are not suitable for applications which require a very small layout area, extremely low power, and a very high operation speed.

General Description

The disclosed method uses a non-symmetrical comparator/sampler circuit structure that introduces a PVT insensitive and well-controlled comparison threshold voltage in the comparator and sampler circuits. See Figures 3a and 3b. This approach not only eliminates the requirement of additional matched pairs for non-zero threshold differential signal comparison/sampling, it also eliminates the need for additional circuits for reference voltage generation. This makes the circuit implementation smaller in area, lower in power usage, and suitable very high frequency operations. The following are three implementations of the disclosed method:

1.      Squelch detection circuit for high-speed serial data communication. In this implementation, the differential peak voltage of a differential input signal of the high-speed receiver is detected. This information is usually used for the receiver to power-on or power-down the circuit. The squelch circuit for such an application is shown in Figure 5. Two non-symm...